On Tue, Feb 4, 2014 at 10:17 AM, Christian König
<deathsimple@xxxxxxxxxxx> wrote:
> From: Christian König <christian.koenig@xxxxxxx>
>
> Only VCE 2.0 support so far.
>
> v2: squashing multiple patches into this one
> v3: add IRQ support for CIK, major cleanups,
> basic code documentation
> v4: remove HAINAN from chipset list
>
> Signed-off-by: Christian König <christian.koenig@xxxxxxx>
> ---
> drivers/gpu/drm/radeon/Makefile | 6 +
> drivers/gpu/drm/radeon/cik.c | 60 ++++
> drivers/gpu/drm/radeon/cikd.h | 33 ++
> drivers/gpu/drm/radeon/radeon.h | 56 +++-
> drivers/gpu/drm/radeon/radeon_asic.c | 17 +
> drivers/gpu/drm/radeon/radeon_asic.h | 13 +
> drivers/gpu/drm/radeon/radeon_cs.c | 4 +
> drivers/gpu/drm/radeon/radeon_kms.c | 1 +
> drivers/gpu/drm/radeon/radeon_ring.c | 4 +
> drivers/gpu/drm/radeon/radeon_test.c | 39 ++-
> drivers/gpu/drm/radeon/radeon_vce.c | 588 +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/radeon/sid.h | 47 +++
> drivers/gpu/drm/radeon/vce_v1_0.c | 187 +++++++++++
> drivers/gpu/drm/radeon/vce_v2_0.c | 70 +++++
> include/uapi/drm/radeon_drm.h | 1 +
> 15 files changed, 1117 insertions(+), 9 deletions(-)
> create mode 100644 drivers/gpu/drm/radeon/radeon_vce.c
> create mode 100644 drivers/gpu/drm/radeon/vce_v1_0.c
> create mode 100644 drivers/gpu/drm/radeon/vce_v2_0.c
>
> diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
> index 306364a..ed60caa 100644
> --- a/drivers/gpu/drm/radeon/Makefile
> +++ b/drivers/gpu/drm/radeon/Makefile
> @@ -99,6 +99,12 @@ radeon-y += \
> uvd_v3_1.o \
> uvd_v4_2.o
>
> +# add VCE block
> +radeon-y += \
> + radeon_vce.o \
> + vce_v1_0.o \
> + vce_v2_0.o \
> +
> radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
> radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
> radeon-$(CONFIG_ACPI) += radeon_acpi.o
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index e6419ca..be6eb4d 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -7490,6 +7490,20 @@ restart_ih:
> /* reset addr and status */
> WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
> break;
> + case 167: /* VCE */
> + DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
> + switch (src_data) {
> + case 0:
> + radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
> + break;
> + case 1:
> + radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
> + break;
> + default:
> + DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
> + break;
> + }
> + break;
> case 176: /* GFX RB CP_INT */
> case 177: /* GFX IB CP_INT */
> radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
> @@ -7789,6 +7803,22 @@ static int cik_startup(struct radeon_device *rdev)
> if (r)
> rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
>
> + r = radeon_vce_resume(rdev);
> + if (!r) {
> + r = vce_v2_0_resume(rdev);
> + if (!r)
> + r = radeon_fence_driver_start_ring(rdev,
> + TN_RING_TYPE_VCE1_INDEX);
> + if (!r)
> + r = radeon_fence_driver_start_ring(rdev,
> + TN_RING_TYPE_VCE2_INDEX);
> + }
> + if (r) {
> + dev_err(rdev->dev, "VCE init error (%d).\n", r);
> + rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
> + rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
> + }
> +
> /* Enable IRQ */
> if (!rdev->irq.installed) {
> r = radeon_irq_kms_init(rdev);
> @@ -7864,6 +7894,23 @@ static int cik_startup(struct radeon_device *rdev)
> DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
> }
>
> + r = -ENOENT;
> +
> + ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
> + if (ring->ring_size)
> + r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
> + VCE_CMD_NO_OP);
> +
> + ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
> + if (ring->ring_size)
> + r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
> + VCE_CMD_NO_OP);
> +
> + if (!r)
> + r = vce_v1_0_init(rdev);
> + else if (r != -ENOENT)
> + DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
> +
> r = radeon_ib_pool_init(rdev);
> if (r) {
> dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
> @@ -7934,6 +7981,7 @@ int cik_suspend(struct radeon_device *rdev)
> cik_sdma_enable(rdev, false);
> uvd_v1_0_fini(rdev);
> radeon_uvd_suspend(rdev);
> + radeon_vce_suspend(rdev);
> cik_fini_pg(rdev);
> cik_fini_cg(rdev);
> cik_irq_suspend(rdev);
> @@ -8066,6 +8114,17 @@ int cik_init(struct radeon_device *rdev)
> r600_ring_init(rdev, ring, 4096);
> }
>
> + r = radeon_vce_init(rdev);
> + if (!r) {
> + ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
> + ring->ring_obj = NULL;
> + r600_ring_init(rdev, ring, 4096);
> +
> + ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
> + ring->ring_obj = NULL;
> + r600_ring_init(rdev, ring, 4096);
> + }
> +
> rdev->ih.ring_obj = NULL;
> r600_ih_ring_init(rdev, 64 * 1024);
>
> @@ -8127,6 +8186,7 @@ void cik_fini(struct radeon_device *rdev)
> radeon_irq_kms_fini(rdev);
> uvd_v1_0_fini(rdev);
> radeon_uvd_fini(rdev);
> + radeon_vce_fini(rdev);
> cik_pcie_gart_fini(rdev);
> r600_vram_scratch_fini(rdev);
> radeon_gem_fini(rdev);
> diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
> index 98bae9d7..459ae02 100644
> --- a/drivers/gpu/drm/radeon/cikd.h
> +++ b/drivers/gpu/drm/radeon/cikd.h
> @@ -2010,4 +2010,37 @@
> /* UVD CTX indirect */
> #define UVD_CGC_MEM_CTRL 0xC0
>
> +/* VCE */
> +
> +#define VCE_VCPU_CACHE_OFFSET0 0x20024
> +#define VCE_VCPU_CACHE_SIZE0 0x20028
> +#define VCE_VCPU_CACHE_OFFSET1 0x2002c
> +#define VCE_VCPU_CACHE_SIZE1 0x20030
> +#define VCE_VCPU_CACHE_OFFSET2 0x20034
> +#define VCE_VCPU_CACHE_SIZE2 0x20038
> +#define VCE_RB_RPTR2 0x20178
> +#define VCE_RB_WPTR2 0x2017c
> +#define VCE_RB_RPTR 0x2018c
> +#define VCE_RB_WPTR 0x20190
> +#define VCE_CLOCK_GATING_A 0x202f8
> +#define VCE_CLOCK_GATING_B 0x202fc
> +#define VCE_UENC_CLOCK_GATING 0x207bc
> +#define VCE_UENC_REG_CLOCK_GATING 0x207c0
> +#define VCE_SYS_INT_EN 0x21300
> +# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
> +#define VCE_LMI_CTRL2 0x21474
> +#define VCE_LMI_CTRL 0x21498
> +#define VCE_LMI_VM_CTRL 0x214a0
> +#define VCE_LMI_SWAP_CNTL 0x214b4
> +#define VCE_LMI_SWAP_CNTL1 0x214b8
> +#define VCE_LMI_CACHE_CTRL 0x214f4
> +
> +#define VCE_CMD_NO_OP 0x00000000
> +#define VCE_CMD_END 0x00000001
> +#define VCE_CMD_IB 0x00000002
> +#define VCE_CMD_FENCE 0x00000003
> +#define VCE_CMD_TRAP 0x00000004
> +#define VCE_CMD_IB_AUTO 0x00000005
> +#define VCE_CMD_SEMAPHORE 0x00000006
> +
> #endif
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index 4a8ac1c..a9295b9 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -113,19 +113,16 @@ extern int radeon_hard_reset;
> #define RADEONFB_CONN_LIMIT 4
> #define RADEON_BIOS_NUM_SCRATCH 8
>
> -/* max number of rings */
> -#define RADEON_NUM_RINGS 6
> -
> /* fence seq are set to this number when signaled */
> #define RADEON_FENCE_SIGNALED_SEQ 0LL
>
> /* internal ring indices */
> /* r1xx+ has gfx CP ring */
> -#define RADEON_RING_TYPE_GFX_INDEX 0
> +#define RADEON_RING_TYPE_GFX_INDEX 0
>
> /* cayman has 2 compute CP rings */
> -#define CAYMAN_RING_TYPE_CP1_INDEX 1
> -#define CAYMAN_RING_TYPE_CP2_INDEX 2
> +#define CAYMAN_RING_TYPE_CP1_INDEX 1
> +#define CAYMAN_RING_TYPE_CP2_INDEX 2
>
> /* R600+ has an async dma ring */
> #define R600_RING_TYPE_DMA_INDEX 3
> @@ -133,7 +130,14 @@ extern int radeon_hard_reset;
> #define CAYMAN_RING_TYPE_DMA1_INDEX 4
>
> /* R600+ */
> -#define R600_RING_TYPE_UVD_INDEX 5
> +#define R600_RING_TYPE_UVD_INDEX 5
> +
> +/* TN+ */
> +#define TN_RING_TYPE_VCE1_INDEX 6
> +#define TN_RING_TYPE_VCE2_INDEX 7
> +
> +/* max number of rings */
> +#define RADEON_NUM_RINGS 8
>
> /* hardcode those limit for now */
> #define RADEON_VA_IB_OFFSET (1 << 20)
> @@ -1589,6 +1593,42 @@ int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
> int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
> unsigned cg_upll_func_cntl);
>
> +/*
> + * VCE
> + */
> +#define RADEON_MAX_VCE_HANDLES 16
> +#define RADEON_VCE_STACK_SIZE (1024*1024)
> +#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
> +
> +struct radeon_vce {
> + struct radeon_bo *vcpu_bo;
> + void *cpu_addr;
> + uint64_t gpu_addr;
> + atomic_t handles[RADEON_MAX_VCE_HANDLES];
> + struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
> +};
> +
> +int radeon_vce_init(struct radeon_device *rdev);
> +void radeon_vce_fini(struct radeon_device *rdev);
> +int radeon_vce_suspend(struct radeon_device *rdev);
> +int radeon_vce_resume(struct radeon_device *rdev);
> +int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
> + uint32_t handle, struct radeon_fence **fence);
> +int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
> + uint32_t handle, struct radeon_fence **fence);
> +void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
> +int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
> +int radeon_vce_cs_parse(struct radeon_cs_parser *p);
> +bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
> + struct radeon_ring *ring,
> + struct radeon_semaphore *semaphore,
> + bool emit_wait);
> +void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
> +void radeon_vce_fence_emit(struct radeon_device *rdev,
> + struct radeon_fence *fence);
> +int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
> +int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
> +
> struct r600_audio_pin {
> int channels;
> int rate;
> @@ -2184,6 +2224,7 @@ struct radeon_device {
> struct radeon_gem gem;
> struct radeon_pm pm;
> struct radeon_uvd uvd;
> + struct radeon_vce vce;
> uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
> struct radeon_wb wb;
> struct radeon_dummy_page dummy_page;
> @@ -2203,6 +2244,7 @@ struct radeon_device {
> const struct firmware *sdma_fw; /* CIK SDMA firmware */
> const struct firmware *smc_fw; /* SMC firmware */
> const struct firmware *uvd_fw; /* UVD firmware */
> + const struct firmware *vce_fw; /* VCE firmware */
> struct r600_vram_scratch vram_scratch;
> int msi_enabled; /* msi enabled */
> struct r600_ih ih; /* r6/700 interrupt ring */
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
> index f74db43..e9eaba99 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.c
> +++ b/drivers/gpu/drm/radeon/radeon_asic.c
> @@ -1987,6 +1987,19 @@ static struct radeon_asic_ring ci_dma_ring = {
> .set_wptr = &cik_sdma_set_wptr,
> };
>
> +static struct radeon_asic_ring ci_vce_ring = {
> + .ib_execute = &radeon_vce_ib_execute,
> + .emit_fence = &radeon_vce_fence_emit,
> + .emit_semaphore = &radeon_vce_semaphore_emit,
> + .cs_parse = &radeon_vce_cs_parse,
> + .ring_test = &radeon_vce_ring_test,
> + .ib_test = &radeon_vce_ib_test,
> + .is_lockup = &radeon_ring_test_lockup,
> + .get_rptr = &vce_v1_0_get_rptr,
> + .get_wptr = &vce_v1_0_get_wptr,
> + .set_wptr = &vce_v1_0_set_wptr,
> +};
> +
> static struct radeon_asic ci_asic = {
> .init = &cik_init,
> .fini = &cik_fini,
> @@ -2015,6 +2028,8 @@ static struct radeon_asic ci_asic = {
> [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
> [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
> [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
> + [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
> + [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
> },
> .irq = {
> .set = &cik_irq_set,
> @@ -2117,6 +2132,8 @@ static struct radeon_asic kv_asic = {
> [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
> [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
> [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
> + [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
> + [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
> },
> .irq = {
> .set = &cik_irq_set,
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
> index b3bc433..2017efd 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.h
> +++ b/drivers/gpu/drm/radeon/radeon_asic.h
> @@ -861,4 +861,17 @@ bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
> /* uvd v4.2 */
> int uvd_v4_2_resume(struct radeon_device *rdev);
>
> +/* vce v1.0 */
> +uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
> + struct radeon_ring *ring);
> +uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
> + struct radeon_ring *ring);
> +void vce_v1_0_set_wptr(struct radeon_device *rdev,
> + struct radeon_ring *ring);
> +int vce_v1_0_init(struct radeon_device *rdev);
> +int vce_v1_0_start(struct radeon_device *rdev);
> +
> +/* vce v2.0 */
> +int vce_v2_0_resume(struct radeon_device *rdev);
> +
> #endif
> diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
> index dfb5a1d..701ee79 100644
> --- a/drivers/gpu/drm/radeon/radeon_cs.c
> +++ b/drivers/gpu/drm/radeon/radeon_cs.c
> @@ -147,6 +147,10 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
> case RADEON_CS_RING_UVD:
> p->ring = R600_RING_TYPE_UVD_INDEX;
> break;
> + case RADEON_CS_RING_VCE:
> + /* TODO: only use the low priority ring for now */
> + p->ring = TN_RING_TYPE_VCE1_INDEX;
> + break;
> }
> return 0;
> }
> diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
> index 114d167..0e078af 100644
> --- a/drivers/gpu/drm/radeon/radeon_kms.c
> +++ b/drivers/gpu/drm/radeon/radeon_kms.c
> @@ -610,6 +610,7 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
> if (rdev->cmask_filp == file_priv)
> rdev->cmask_filp = NULL;
> radeon_uvd_free_handles(rdev, file_priv);
> + radeon_vce_free_handles(rdev, file_priv);
> }
>
> /*
> diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
> index 1b783f0..149cd63 100644
> --- a/drivers/gpu/drm/radeon/radeon_ring.c
> +++ b/drivers/gpu/drm/radeon/radeon_ring.c
> @@ -814,6 +814,8 @@ static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
> static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
> static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
> static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
> +static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
> +static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
>
> static struct drm_info_list radeon_debugfs_ring_info_list[] = {
> {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
> @@ -822,6 +824,8 @@ static struct drm_info_list radeon_debugfs_ring_info_list[] = {
> {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
> {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
> {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
> + {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
> + {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
> };
>
> static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
> diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
> index 12e8099..3a13e0d 100644
> --- a/drivers/gpu/drm/radeon/radeon_test.c
> +++ b/drivers/gpu/drm/radeon/radeon_test.c
> @@ -257,20 +257,36 @@ static int radeon_test_create_and_emit_fence(struct radeon_device *rdev,
> struct radeon_ring *ring,
> struct radeon_fence **fence)
> {
> + uint32_t handle = ring->idx ^ 0xdeafbeef;
> int r;
>
> if (ring->idx == R600_RING_TYPE_UVD_INDEX) {
> - r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
> + r = radeon_uvd_get_create_msg(rdev, ring->idx, handle, NULL);
> if (r) {
> DRM_ERROR("Failed to get dummy create msg\n");
> return r;
> }
>
> - r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, fence);
> + r = radeon_uvd_get_destroy_msg(rdev, ring->idx, handle, fence);
> if (r) {
> DRM_ERROR("Failed to get dummy destroy msg\n");
> return r;
> }
> +
> + } else if (ring->idx == TN_RING_TYPE_VCE1_INDEX ||
> + ring->idx == TN_RING_TYPE_VCE2_INDEX) {
> + r = radeon_vce_get_create_msg(rdev, ring->idx, handle, NULL);
> + if (r) {
> + DRM_ERROR("Failed to get dummy create msg\n");
> + return r;
> + }
> +
> + r = radeon_vce_get_destroy_msg(rdev, ring->idx, handle, fence);
> + if (r) {
> + DRM_ERROR("Failed to get dummy destroy msg\n");
> + return r;
> + }
> +
> } else {
> r = radeon_ring_lock(rdev, ring, 64);
> if (r) {
> @@ -486,6 +502,16 @@ out_cleanup:
> printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
> }
>
> +static bool radeon_test_sync_possible(struct radeon_ring *ringA,
> + struct radeon_ring *ringB)
> +{
> + if (ringA->idx == TN_RING_TYPE_VCE2_INDEX &&
> + ringB->idx == TN_RING_TYPE_VCE1_INDEX)
> + return false;
> +
> + return true;
> +}
> +
> void radeon_test_syncing(struct radeon_device *rdev)
> {
> int i, j, k;
> @@ -500,6 +526,9 @@ void radeon_test_syncing(struct radeon_device *rdev)
> if (!ringB->ready)
> continue;
>
> + if (!radeon_test_sync_possible(ringA, ringB))
> + continue;
> +
> DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
> radeon_test_ring_sync(rdev, ringA, ringB);
>
> @@ -511,6 +540,12 @@ void radeon_test_syncing(struct radeon_device *rdev)
> if (!ringC->ready)
> continue;
>
> + if (!radeon_test_sync_possible(ringA, ringC))
> + continue;
> +
> + if (!radeon_test_sync_possible(ringB, ringC))
> + continue;
> +
> DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
> radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
>
> diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c
> new file mode 100644
> index 0000000..2547d8e
> --- /dev/null
> +++ b/drivers/gpu/drm/radeon/radeon_vce.c
> @@ -0,0 +1,588 @@
> +/*
> + * Copyright 2013 Advanced Micro Devices, Inc.
> + * All Rights Reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction, including
> + * without limitation the rights to use, copy, modify, merge, publish,
> + * distribute, sub license, and/or sell copies of the Software, and to
> + * permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
> + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> + * USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + * Authors: Christian König <christian.koenig@xxxxxxx>
> + */
> +
> +#include <linux/firmware.h>
> +#include <linux/module.h>
> +#include <drm/drmP.h>
> +#include <drm/drm.h>
> +
> +#include "radeon.h"
> +#include "radeon_asic.h"
> +#include "sid.h"
> +
> +/* Firmware Names */
> +#define FIRMWARE_BONAIRE "radeon/BONAIRE_vce.bin"
> +
> +MODULE_FIRMWARE(FIRMWARE_BONAIRE);
> +
> +/**
> + * radeon_vce_init - allocate memory, load vce firmware
> + *
> + * @rdev: radeon_device pointer
> + *
> + * First step to get VCE online, allocate memory and load the firmware
> + */
> +int radeon_vce_init(struct radeon_device *rdev)
> +{
> + unsigned long bo_size;
> + const char *fw_name;
> + int i, r;
> +
> + switch (rdev->family) {
> + case CHIP_BONAIRE:
> + case CHIP_KAVERI:
> + case CHIP_KABINI:
Missing a case for HAWAII here.
Alex
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