I made some minor cleanups and also added a missing 7xx reg to the
safe regs list.
Alex
On Wed, Jan 29, 2014 at 11:11 PM, Dave Airlie <airlied@xxxxxxxxx> wrote:
> From: Dave Airlie <airlied@xxxxxxxxxx>
>
> the evergreen CS parser has allowed this for a while, just port
> the code to the r600 one.
>
> This is required before geom shaders can be made work.
>
> Signed-off-by: Dave Airlie <airlied@xxxxxxxxxx>
> ---
> drivers/gpu/drm/radeon/r600_cs.c | 18 ++++++++++++++++--
> drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
> index 7b399dc..98e1f6b 100644
> --- a/drivers/gpu/drm/radeon/r600_cs.c
> +++ b/drivers/gpu/drm/radeon/r600_cs.c
> @@ -1007,8 +1007,22 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
> case R_008C64_SQ_VSTMP_RING_SIZE:
> case R_0288C8_SQ_GS_VERT_ITEMSIZE:
> /* get value to populate the IB don't remove */
> - tmp =radeon_get_ib_value(p, idx);
> - ib[idx] = 0;
> + // tmp =radeon_get_ib_value(p, idx);
> + // ib[idx] = 0;
> + break;
> + case SQ_ESGS_RING_BASE:
> + case SQ_GSVS_RING_BASE:
> + case SQ_ESTMP_RING_BASE:
> + case SQ_GSTMP_RING_BASE:
> + case SQ_PSTMP_RING_BASE:
> + case SQ_VSTMP_RING_BASE:
> + r = radeon_cs_packet_next_reloc(p, &reloc, 0);
> + if (r) {
> + dev_warn(p->dev, "bad SET_CONTEXT_REG "
> + "0x%04X\n", reg);
> + return -EINVAL;
> + }
> + ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
> break;
> case SQ_CONFIG:
> track->sq_config = radeon_get_ib_value(p, idx);
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
> index ec8c388..357cffb 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -78,9 +78,10 @@
> * 2.34.0 - Add CIK tiling mode array query
> * 2.35.0 - Add CIK macrotile mode array query
> * 2.36.0 - Fix CIK DCE tiling setup
> + * 2.37.0 - allow ring setup on r6xx/r7xx
> */
> #define KMS_DRIVER_MAJOR 2
> -#define KMS_DRIVER_MINOR 36
> +#define KMS_DRIVER_MINOR 37
> #define KMS_DRIVER_PATCHLEVEL 0
> int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
> int radeon_driver_unload_kms(struct drm_device *dev);
> --
> 1.8.3.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
From 4c79afe26e0aace9fc1497b72db4508308f91f08 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@xxxxxxxxxx>
Date: Thu, 30 Jan 2014 14:11:12 +1000
Subject: [PATCH] drm/radeon: allow geom rings to be setup on r600/r700 (v2)
the evergreen CS parser has allowed this for a while, just port
the code to the r600 one.
This is required before geom shaders can be made work.
v2: agd5f: minor cleanup and add additional 7xx reg.
Signed-off-by: Dave Airlie <airlied@xxxxxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/radeon/r600_cs.c | 18 ++++++++++++++++--
drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
drivers/gpu/drm/radeon/reg_srcs/r600 | 1 +
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 7b399dc..2812c7d1a 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -1007,8 +1007,22 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
case R_008C64_SQ_VSTMP_RING_SIZE:
case R_0288C8_SQ_GS_VERT_ITEMSIZE:
/* get value to populate the IB don't remove */
- tmp =radeon_get_ib_value(p, idx);
- ib[idx] = 0;
+ /*tmp =radeon_get_ib_value(p, idx);
+ ib[idx] = 0;*/
+ break;
+ case SQ_ESGS_RING_BASE:
+ case SQ_GSVS_RING_BASE:
+ case SQ_ESTMP_RING_BASE:
+ case SQ_GSTMP_RING_BASE:
+ case SQ_PSTMP_RING_BASE:
+ case SQ_VSTMP_RING_BASE:
+ r = radeon_cs_packet_next_reloc(p, &reloc, 0);
+ if (r) {
+ dev_warn(p->dev, "bad SET_CONTEXT_REG "
+ "0x%04X\n", reg);
+ return -EINVAL;
+ }
+ ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
break;
case SQ_CONFIG:
track->sq_config = radeon_get_ib_value(p, idx);
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index ec8c388..84a1bbb7 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -78,9 +78,10 @@
* 2.34.0 - Add CIK tiling mode array query
* 2.35.0 - Add CIK macrotile mode array query
* 2.36.0 - Fix CIK DCE tiling setup
+ * 2.37.0 - allow GS ring setup on r6xx/r7xx
*/
#define KMS_DRIVER_MAJOR 2
-#define KMS_DRIVER_MINOR 36
+#define KMS_DRIVER_MINOR 37
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index 20bfbda..ec0c682 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -18,6 +18,7 @@ r600 0x9400
0x00028A3C VGT_GROUP_VECT_1_FMT_CNTL
0x00028A40 VGT_GS_MODE
0x00028A6C VGT_GS_OUT_PRIM_TYPE
+0x00028B38 VGT_GS_MAX_VERT_OUT
0x000088C8 VGT_GS_PER_ES
0x000088E8 VGT_GS_PER_VS
0x000088D4 VGT_GS_VERTEX_REUSE
--
1.8.3.1
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