On Mon, Feb 17, 2025 at 05:41:33PM +0100, Krzysztof Kozlowski wrote: > Add support for DSI on Qualcomm SM8750 SoC with notable difference: > > DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as > parents before DSI PHY is configured and the PLLs are prepared with > initial rate is set. Therefore assigned-clock-parents are not working > here and driver is responsible for reparenting clocks with proper > procedure: see dsi_clk_init_6g_v2_9(). > > Part of the change is exactly the same as CLK_OPS_PARENT_ENABLE, however > CLK_OPS_PARENT_ENABLE won't work here because assigned-clock-parents are > executed way too early - before DSI PHY is configured. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > --- > > SM8750 DSI PHY also needs Dmitry's patch: > https://patchwork.freedesktop.org/patch/542000/?series=119177&rev=1 > (or some other way of correct early setting of the DSI PHY PLL rate) > --- > drivers/gpu/drm/msm/dsi/dsi.h | 2 + > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 25 ++++++++++++ > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + > drivers/gpu/drm/msm/dsi/dsi_host.c | 80 ++++++++++++++++++++++++++++++++++++++ > 4 files changed, 108 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h > index 87496db203d6c7582eadcb74e94eb56a219df292..93c028a122f3a59b1632da76472e0a3e781c6ae8 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi.h > +++ b/drivers/gpu/drm/msm/dsi/dsi.h > @@ -98,6 +98,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); > int msm_dsi_runtime_suspend(struct device *dev); > int msm_dsi_runtime_resume(struct device *dev); > int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host); > +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host); > int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host); > int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host); > int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host); > @@ -115,6 +116,7 @@ int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *iova); > int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova); > int dsi_clk_init_v2(struct msm_dsi_host *msm_host); > int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); > +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host); > int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi); > int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi); > void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host); > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > index 7754dcec33d06e3d6eb8a9d55e53f24af073adb9..e2a8d6fcc45b6c207a3018ea7c8744fcf34dabd2 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > @@ -205,6 +205,17 @@ static const struct msm_dsi_config sm8650_dsi_cfg = { > }, > }; > > +static const struct msm_dsi_config sm8750_dsi_cfg = { Can we use sm8650_dsi_cfg instead? What is the difference? > + .io_offset = DSI_6G_REG_SHIFT, > + .regulator_data = sm8650_dsi_regulators, > + .num_regulators = ARRAY_SIZE(sm8650_dsi_regulators), > + .bus_clk_names = dsi_v2_4_clk_names, > + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), > + .io_start = { > + { 0xae94000, 0xae96000 }, > + }, > +}; > + The rest LGTM. I'm not very happy regarding the clock handling, but it seems we jave to live with it. -- With best wishes Dmitry
