Hi Dave, Please do _not_ pull this. The pipe bpp readout stuff this crucially relies on is only partially backported from -next to -fixes and apparently missing bits on Haswell. Thanks, Daniel On Fri, Oct 25, 2013 at 12:50:12PM +0200, Daniel Vetter wrote: > Hi Dave, > > Just the edp bpp fix from Jani plus the pipe bpp readout code from Ville > to make it work. There's a 3 pipe ivb regression fix pending from me, but > Ville's review convinced me that my first stab is broken. > > Cheers, Daniel > > > The following changes since commit 828c79087cec61eaf4c76bb32c222fbe35ac3930: > > drm/i915: Disable GGTT PTEs on GEN6+ suspend (2013-10-18 15:44:47 +0200) > > are available in the git repository at: > > git://people.freedesktop.org/~danvet/drm-intel tags/drm-intel-fixes-2013-10-25 > > for you to fetch changes up to 52e1e223456e3aa747e9932f95948381f04b3b26: > > drm/i915/dp: workaround BIOS eDP bpp clamping issue (2013-10-21 > 09:57:02 +0200) > > ---------------------------------------------------------------- > Jani Nikula (1): > drm/i915/dp: workaround BIOS eDP bpp clamping issue > > Ville Syrjälä (1): > drm/i915: Add support for pipe_bpp readout > > drivers/gpu/drm/i915/intel_ddi.c | 17 +++++++++++++++++ > drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++++ > 3 files changed, 73 insertions(+) > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
