Regards, Suraj Kandpal > /* Enable histogram interrupt */ > intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), > DPST_GUARD_HIST_INT_EN, > DPST_GUARD_HIST_INT_EN); > @@ -240,6 +251,12 @@ int intel_histogram_set_iet_lut(struct intel_crtc > *intel_crtc, u32 *data) > return -EINVAL; > } > > + /* Wa: 14014889975 */ > + if (IS_DISPLAY_VER(display, 12, 13)) > + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt > Delay Counter(bit 23:16) */ > + intel_de_write(display, DPST_CTL(intel_crtc->pipe), > intel_de_read(display, > + DPST_CTL(intel_crtc->pipe)) | > DPST_CTL_RESTORE); > + > /* > * Set DPST_CTL Bin Reg function select to IE > * Set DPST_CTL Bin Register Index to 0 diff --git > a/drivers/gpu/drm/i915/display/intel_histogram_regs.h > b/drivers/gpu/drm/i915/display/intel_histogram_regs.h > index 1252b4f339a6..e50b1448bd40 100644 > --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h > @@ -16,6 +16,7 @@ > #define DPST_CTL_RESTORE REG_BIT(28) > #define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) > #define DPST_CTL_HIST_MODE REG_BIT(24) > +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT > REG_GENMASK(23, 16) > #define DPST_CTL_ENHANCEMENT_MODE_MASK > REG_GENMASK(14, 13) > #define DPST_CTL_EN_MULTIPLICATIVE > REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) > #define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) > -- > 2.25.1
