Hi shiyongbang, kernel test robot noticed the following build errors: [auto build test ERROR on drm-misc/drm-misc-next] [also build test ERROR on linus/master v6.12-rc1 next-20241003] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/shiyongbang/drm-hisilicon-hibmc-add-dp-aux-in-hibmc-drivers/20240930-181437 base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next patch link: https://lore.kernel.org/r/20240930100610.782363-3-shiyongbang%40huawei.com patch subject: [PATCH drm-dp 2/4] drm/hisilicon/hibmc: add dp link moduel in hibmc drivers config: i386-buildonly-randconfig-003-20241003 (https://download.01.org/0day-ci/archive/20241003/202410031735.8iRZZR6T-lkp@xxxxxxxxx/config) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241003/202410031735.8iRZZR6T-lkp@xxxxxxxxx/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@xxxxxxxxx> | Closes: https://lore.kernel.org/oe-kbuild-all/202410031735.8iRZZR6T-lkp@xxxxxxxxx/ All errors (new ones prefixed by >>): In file included from drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c:10: drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c: In function 'dp_link_training_cr_pre': >> drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.h:45:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] 45 | #define DPCD_VOLTAGE_SWING_LEVEL_2 FIELD_PREP(GENMASK(1, 0), 2) | ^~~~~~~~~~ drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c:105:32: note: in expansion of macro 'DPCD_VOLTAGE_SWING_LEVEL_2' 105 | train_set[i] = DPCD_VOLTAGE_SWING_LEVEL_2 | DPCD_PRE_EMPHASIS_LEVEL_0; | ^~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: some warnings being treated as errors vim +/FIELD_PREP +45 drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.h ff6e8ef6021188 baihan li 2024-09-30 37 ff6e8ef6021188 baihan li 2024-09-30 38 #define DPCD_TRAINING_PATTERN_DISABLE 0x0 ff6e8ef6021188 baihan li 2024-09-30 39 #define DPCD_TRAINING_PATTERN_1 0x1 ff6e8ef6021188 baihan li 2024-09-30 40 #define DPCD_TRAINING_PATTERN_2 0x2 ff6e8ef6021188 baihan li 2024-09-30 41 #define DPCD_TRAINING_PATTERN_3 0x3 ff6e8ef6021188 baihan li 2024-09-30 42 #define DPCD_TRAINING_PATTERN_4 0x7 ff6e8ef6021188 baihan li 2024-09-30 43 #define DPCD_VOLTAGE_SWING_LEVEL_0 FIELD_PREP(GENMASK(1, 0), 0) ff6e8ef6021188 baihan li 2024-09-30 44 #define DPCD_VOLTAGE_SWING_LEVEL_1 FIELD_PREP(GENMASK(1, 0), 1) ff6e8ef6021188 baihan li 2024-09-30 @45 #define DPCD_VOLTAGE_SWING_LEVEL_2 FIELD_PREP(GENMASK(1, 0), 2) ff6e8ef6021188 baihan li 2024-09-30 46 #define DPCD_VOLTAGE_SWING_LEVEL_3 FIELD_PREP(GENMASK(1, 0), 3) ff6e8ef6021188 baihan li 2024-09-30 47 #define DPCD_PRE_EMPHASIS_LEVEL_0 FIELD_PREP(GENMASK(4, 3), 0) ff6e8ef6021188 baihan li 2024-09-30 48 #define DPCD_PRE_EMPHASIS_LEVEL_1 FIELD_PREP(GENMASK(4, 3), 1) ff6e8ef6021188 baihan li 2024-09-30 49 #define DPCD_PRE_EMPHASIS_LEVEL_2 FIELD_PREP(GENMASK(4, 3), 2) ff6e8ef6021188 baihan li 2024-09-30 50 #define DPCD_PRE_EMPHASIS_LEVEL_3 FIELD_PREP(GENMASK(4, 3), 3) ff6e8ef6021188 baihan li 2024-09-30 51 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
