Comment # 12
on bug 69723
from Alexandre Demers
(In reply to comment #11) > (In reply to comment #10) > > Just to be sure: vddc is associated only to sclk and vddci to mclk, right? > > > > Not exactly. Mclk is tied to vddci (memory interface voltage), but both > mclk and sclk (and the core display clock) are tied to vddc (core voltage). > > > Also, how are a new freq and a new voltage applied to the card? Are they > > applied simultanously or sequentially? In the second case, we must be sure > > to raise voltage before frequency when pushing the performances up, while we > > should low the frequency before lowering the voltage when we are slowing > > down. > > The actual adjustments are done by a microcontroller on the GPU. You pass a > set of structures defining the performance levels within the power state to > the microcontroller and the microcontroller handles the switching. It takes > into account all of the ordering and chip state dependencies. I was asking, just in case there was a manual control over the process and I would have been in a situation where the card was too near of its limits. I changed a little something in the code yesterday and I was lucky enough to not have any hangs. I just want to be sure it is because of this little change I've made and not some obscure planets alignment. I'll test it further today and I'll let you know.
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