Hi Jocelyn
Am 08.07.24 um 14:46 schrieb Jocelyn Falempe:
On 05/07/2024 13:47, Thomas Zimmermann wrote:
There's no VBLANK interrupt on Matrox chipsets. The workaround that is
being used here and in other free Matrox drivers is to program
<linecomp>
to the value of <vblkstr> and enable the VLINE interrupt. This triggers
an interrupt at the time when VBLANK begins.
VLINE uses separate registers for enabling and clearing pending
interrupts.
No extra synchronization between irq handler and the rest of the
driver is
required.
Thanks for this patch, I have a few comments below:
They make sense. I'll implement them.
[...]
#define MGAREG_IEN 0x1e1c
+#define MGAREG_IEN_VLINEIEN BIT(5)
#define MGAREG_VCOUNT 0x1e20
Do you know what happens if the IRQ doesn't work (ie not receiving any
IRQ)?
We'd miss the vblank timeout and the display would be slow or static.
When testing the DMA, I remember that on a few machines, I never get
the Softrap IRQ. I don't know if it was a DMA engine problem, or if
it's the mgag200 IRQ that was not connected properly.
What to do depends. Not having an IRQ assigned is a problem in the BIOS
configuration. All other DRM drivers expect the IRQ to be present and
mgag200 would not be any different here. Users should assign an IRQ in
BIOS. If there's really a hardware problem on some Matrox chips, we'd
have to revert the patch. There's little use in handling separate vblank
and non-vblank code paths. Most other patches in this patchset would
still remain useful, I think.
OTOH other Matrox drivers have implemented vblank support since forever.
I'd expect (well, hope at least :) that this simply isn't a problem.
I will try to find this machine, and test this series on it.
Thanks a lot.
Best regards
Thomas
Best regards,
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
