On Wed, Sep 18, 2013 at 9:39 AM, Michel Dänzer <michel@xxxxxxxxxxx> wrote: > From: Michel Dänzer <michel.daenzer@xxxxxxx> > > Signed-off-by: Michel Dänzer <michel.daenzer@xxxxxxx> > --- > > Not sure this is necessary, but AFAICT the pipe configuration applies to > 1D tiling modes as well. I don't think pipe config applies to 1D modes since they are fixed size across asics. > > drivers/gpu/drm/radeon/cik.c | 48 +++++++++++++++++++++++++++++--------------- > 1 file changed, 32 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index 8feaf51..35d8247 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -1788,7 +1788,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 5: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); > break; > case 6: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -1808,7 +1809,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 9: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); > break; > case 10: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -1830,7 +1832,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 13: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); > break; > case 14: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -1852,7 +1855,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 27: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); > break; > case 28: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2007,7 +2011,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 5: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_16x16); > break; > case 6: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2027,7 +2032,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 9: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_16x16); > break; > case 10: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2049,7 +2055,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 13: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_16x16); > break; > case 14: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2071,7 +2078,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 27: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_16x16); > break; > case 28: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2133,7 +2141,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 5: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16); > break; > case 6: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2153,7 +2162,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 9: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16); > break; > case 10: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2175,7 +2185,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 13: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16); > break; > case 14: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2197,7 +2208,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 27: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16); > break; > case 28: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2352,7 +2364,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 5: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P2); > break; > case 6: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2371,7 +2384,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 9: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P2); > break; > case 10: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2393,7 +2407,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 13: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P2); > break; > case 14: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2415,7 +2430,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 27: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P2); > break; > case 28: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > -- > 1.8.4.rc3 > > _______________________________________________ > dri-devel mailing list > dri-devel@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
