If the low and high sclks within a power state are the same,
there no need to enable sclk scaling. Enabling sclk scaling
can cause display stability issues on some boards.
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/radeon/rs780_dpm.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c b/drivers/gpu/drm/radeon/rs780_dpm.c
index eb336bf..6af8505 100644
--- a/drivers/gpu/drm/radeon/rs780_dpm.c
+++ b/drivers/gpu/drm/radeon/rs780_dpm.c
@@ -1043,8 +1043,10 @@ int rs780_dpm_force_performance_level(struct radeon_device *rdev,
if (pi->voltage_control)
rs780_force_voltage(rdev, pi->max_voltage);
- WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
- rs780_clk_scaling_enable(rdev, true);
+ if (ps->sclk_high != ps->sclk_low) {
+ WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
+ rs780_clk_scaling_enable(rdev, true);
+ }
if (pi->voltage_control) {
rs780_voltage_scaling_enable(rdev, true);
--
1.8.3.1
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