Hello all,
This series provides some crucial fixes and improvements for the Cadence's DSI
TX (cdns-dsi) controller found commonly in Texas Instruments' J7 family of SoCs
as well as in AM62P.
Along with that, this series aims to fix the color-shift issue that has been
going on with the DSI controller. This controller requires to be enabled before
the previous entity enables its stream[0]. It's a strict requirement which, if
not followed, causes the colors to "shift" on the display. The fix happens in
2 steps.
1. The bridge pre_enable calls have been shifted before the crtc_enable and
the bridge post_disable calls have been shifted after the crtc_disable.
This has been done as per the definition of bridge pre_enable.
"The display pipe (i.e. clocks and timing signals) feeding this bridge
will not yet be running when this callback is called".
Since CRTC is also a source feeding the bridge, it should not be enabled
before the bridges in the pipeline are pre_enabled.
The sequence of enable after this patch will look like:
bridge[n]_pre_enable
...
bridge[1]_pre_enable
crtc_enable
encoder_enable
bridge[1]_enable
...
bridge[n]_enable
and vice-versa for the bridge chain disable sequence.
2. The cdns-dsi enable / disable sequences have now been moved to pre_enable
and post_disable sequences. This is the only way to have cdns-dsi drivers
be up and ready before the previous entity is enables its streaming.
The DSI also spec requires the Clock and Data Lanes be ready before the DSI TX
enables its stream[0]. A patch has been added to make the code wait for that to
happen. Going ahead with further DSI (and DSS configuration), while the lanes
are not ready, has been found to be another reason for shift in colors.
All these patches have been tested on TI's vendor tree kernel with more devices,
but for the mainline, these patches have been tested with J721E based
BeagleboneAI64 along with a RaspberryPi 7" DSI panel. The extra patches can be
found in the "next_dsi-v2-tests" branch of my github fork[1] for anyone who
would like to test them.
Thanks,
Aradhya
[0]: Section 12.6.5.7.3: "Start-up Procedure" [For DSI TX controller]
in TDA4VM Technical Reference Manual https://www.ti.com/lit/zip/spruil1
[1]: https://github.com/aradhya07/linux-ab/tree/next_dsi-v2-tests
Change Log:
- Changes in v2:
- Drop patch "drm/tidss: Add CRTC mode_fixup"
- Split patch "drm/bridge: cdns-dsi: Fix minor bugs" into 4 separate ones
- Drop support for early_enable/late_disable APIs and instead re-order the
pre_enable / post_disable APIs to be called before / after crtc_enable /
crtc_disable.
- Drop support for early_enable/late_disable in cdns-dsi and use
pre_enable/post_disable APIs instead to do bridge enable/disable.
Previous versions:
v1: https://lore.kernel.org/all/20240511153051.1355825-1-a-bhatia1@xxxxxx/
Aradhya Bhatia (9):
drm/bridge: cdns-dsi: Fix OF node pointer
drm/bridge: cdns-dsi: Fix the phy_initialized variable
drm/bridge: cdns-dsi: Fix the link and phy init order
drm/bridge: cdns-dsi: Fix the clock variable for mode_valid()
drm/bridge: cdns-dsi: Wait for Clk and Data Lanes to be ready
drm/bridge: cdns-dsi: Reset the DCS write FIFO
drm/bridge: cdns-dsi: Support atomic bridge APIs
drm/atomic-helper: Re-order bridge chain pre-enable and post-disable
drm/bridge: cdns-dsi: Use pre_enable/post_disable to enable/disable
.../gpu/drm/bridge/cadence/cdns-dsi-core.c | 91 ++++++++++++++-----
drivers/gpu/drm/drm_atomic_helper.c | 70 +++++++++++++-
2 files changed, 135 insertions(+), 26 deletions(-)
base-commit: 9d99040b1bc8dbf385a8aa535e9efcdf94466e19
--
2.34.1
