The MFG_ASYNC domain, which is likely associated to the whole MFG block,
currently specifies clk26m as its domain clock. This is bogus, since the
clock is an external crystal with no controls. Also, the MFG block has
a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
diagram, gates access to the hardware registers. Having this one as the
domain clock makes much more sense. This also fixes access to the MFGTOP
registers.
Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL.
Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller")
Signed-off-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 3458be7f7f61..136b28f80cc2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -497,7 +497,7 @@ power-domain@MT8173_POWER_DOMAIN_USB {
};
mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
- clocks = <&clk26m>;
+ clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
--
2.45.1.288.g0e0cd299f1-goog
