The vendor kernel sets a previously unknown clock gating bit in the
VIVS_PM_MODULE_CONTROLS register to disable SH_EU clock gating.
Import new headers from rnndb for the definition and set the bit
for the VIPNano-Si+ NPU on i.MX8MP.
Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
---
Philipp Zabel (2):
drm/etnaviv: Update hardware headers from rnndb
drm/etnaviv: Disable SH_EU clock gating on VIPNano-Si+
drivers/gpu/drm/etnaviv/cmdstream.xml.h | 52 ++++++++++++++--
drivers/gpu/drm/etnaviv/common.xml.h | 12 ++--
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 4 ++
drivers/gpu/drm/etnaviv/state.xml.h | 101 +++++++++++++++++++++++++++-----
drivers/gpu/drm/etnaviv/state_blt.xml.h | 20 +++----
drivers/gpu/drm/etnaviv/state_hi.xml.h | 28 +++++----
6 files changed, 174 insertions(+), 43 deletions(-)
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240124-etnaviv-npu-627f6881322c
Best regards,
--
Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
