> The hs_rate and lp_rate may be used by the dsi host for timing > calculations. The tc358775 has a maximum bit rate of 1 Gbps/lane, > tc358765 has maximurate of 800 Mbps per lane. > > Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx> > --- > drivers/gpu/drm/bridge/tc358775.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c > --- a/drivers/gpu/drm/bridge/tc358775.c > +++ b/drivers/gpu/drm/bridge/tc358775.c > @@ -636,6 +636,11 @@ static int tc_attach_host(struct tc_data *tc) > dsi->format = MIPI_DSI_FMT_RGB888; > dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | > MIPI_DSI_MODE_LPM; > + if (tc->type == TC358765) > + dsi->hs_rate = 800000000; It's not clear to me whether this is the data rate or the frequency. From the kernel doc: * @hs_rate: maximum lane frequency for high speed mode in hertz, this should * be set to the real limits of the hardware, zero is only accepted for * legacy drivers The tc358775 datasheet lists 1Gbps per lane, which corresponds to a 500MHz DSI clock frequency. Not sure how that would correspond to the "maximum lane frequency" above. I guess the wording of the comment is just misleading and the value is the data rate of the lane. > + else > + dsi->hs_rate = 1000000000; > + dsi->lp_rate = 10000000; That I didn't found in the datasheet. Just a T_min_rx (minimum pulse width response) which is 20ns. But there are no more details on this. -michael
