Comment # 1
on bug 66384
from Michel Dänzer
I think this is because the DRI2 MSC counters differ between CRTCs, so a DRI2 buffer swap or MSC wait times out. AFAICT it might be tricky to fix this, at least without DRI3.
You are receiving this mail because:
- You are the assignee for the bug.
_______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
