On Mon, 28 Aug 2023 13:17:44 -0500, Adam Ford wrote:
> On Mon, Aug 28, 2023 at 11:42 AM Marco Felsch <m.felsch@xxxxxxxxxxxxxx> wrote:
> >
> > On 23-08-28, Michael Tretter wrote:
> > > The PLL requires a clock between 2 MHz and 30 MHz after the pre-divider.
> > > The reference clock for the PLL may change due to changes to it's parent
> > > clock. Thus, the frequency may be out of range or unsuited for
> > > generating the high speed clock for MIPI DSI.
> > >
> > > Try to keep the pre-devider small, and set the reference clock close to
> > > 30 MHz before recalculating the PLL configuration. Use a divider with a
> > > power of two for the reference clock as this seems to work best in
> > > my tests.
> > >
> > > Signed-off-by: Michael Tretter <m.tretter@xxxxxxxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/bridge/samsung-dsim.c | 15 +++++++++++++--
> > > 1 file changed, 13 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> > > index da90c2038042..4de6e4f116db 100644
> > > --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> > > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> > > @@ -611,10 +611,21 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
> > > u16 m;
> > > u32 reg;
> > >
> > > - if (dsi->pll_clk)
> > > + if (dsi->pll_clk) {
> > > + /*
> > > + * Ensure that the reference clock is generated with a power of
> > > + * two divider from its parent, but close to the PLLs upper
> > > + * limit of the valid range of 2 MHz to 30 MHz.
> > > + */
> > > + fin = clk_get_rate(clk_get_parent(dsi->pll_clk));
> > > + while (fin > 30 * MHZ)
> > > + fin = fin / 2;
> >
> > Really just a cosmetic nit: fin /= 2;
> >
> > Reviewed-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
> >
> > > + clk_set_rate(dsi->pll_clk, fin);
> > > +
> > > fin = clk_get_rate(dsi->pll_clk);
> > > - else
> > > + } else {
> > > fin = dsi->pll_clk_rate;
> > > + }
>
> I don't have all the code style rules memorized. Did you run it
> through checkpatch? I wonder if the braces here are appropriate for a
> 1-line after the else. If checkpatch is happy, I am fine with it.
checkpatch is happy: The coding style states that if one of the branches needs
braces because it has multiple statements, all branches should have braces.
Michael
>
> adam
> > > dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin);
> > >
> > > fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
> > >
> > > --
> > > 2.39.2
> > >
> > >
> > >
>
