On Thu, 2023-07-06 at 12:26 +0200, AngeloGioacchino Del Regno wrote:
This patch is for MT8188 hw design change, MT8195 has not changed, so MT8195 does not need modify.
Best Regards,
Shuijing
> 1.The audio packet arrangement function is to only arrange audio> packets into the Hblanking area. In order to align with the HW> default setting of g1200, this function needs to be turned off.>> 2.Due to the difference of HW, different dividers need to be set.>> Signed-off-by: Shuijing Li <shuijing.li@xxxxxxxxxxxx>> Signed-off-by: Jitao Shi <jitao.shi@xxxxxxxxxxxx>> ---> Changes in v2:> - change the variables' name to be more descriptive> - add a comment that describes the function of mtk_dp_audio_sample_arrange> - reduce indentation by doing the inverse check> - add a definition of some bits> - add support for mediatek, mt8188-edp-tx> per suggestion from the previous thread:> https://lore.kernel.org/lkml/ac0fcec9-a2fe-06cc-c727-189ef7babe9c@xxxxxxxxxxxxx/> ---> drivers/gpu/drm/mediatek/mtk_dp.c | 47 ++++++++++++++++++++++++++-> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 6 ++++> 2 files changed, 52 insertions(+), 1 deletion(-)>> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c> index 64eee77452c0..8e1a13ab2ba2 100644> --- a/drivers/gpu/drm/mediatek/mtk_dp.c> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c> @@ -139,6 +139,8 @@ struct mtk_dp_data {> unsigned int smc_cmd;> const struct mtk_dp_efuse_fmt *efuse_fmt;> bool audio_supported;> +bool audio_pkt_in_hblank_area;> +u16 audio_m_div2_bit;> };>> static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {> @@ -647,7 +649,7 @@ static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp,> static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp)> {> mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,> - AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,> + mtk_dp->data->audio_m_div2_bit,> AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);> }>> @@ -1362,6 +1364,18 @@ static void mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)> SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);> }>> +static void mtk_dp_audio_sample_arrange(struct mtk_dp *mtk_dp)> +{> +/* arrange audio packets into the Hblanking and Vblanking area */> +if (!mtk_dp->data->audio_pkt_in_hblank_area)> +return;There's only one remaining question: why is this done for MT8188 but *not* forMT8195?Thanks,Angelo> +> +mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,> + SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK);> +mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,> + SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK);> +}> +> static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)> {> u32 sram_read_start = min_t(u32, MTK_DP_TBC_BUF_READ_START_ADDR,> @@ -1371,6 +1385,7 @@ static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)> MTK_DP_PIX_PER_ADDR);> mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);> mtk_dp_setup_encoder(mtk_dp);> +mtk_dp_audio_sample_arrange(mtk_dp);> mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp);> mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start);> }> @@ -2616,11 +2631,31 @@ static int mtk_dp_resume(struct device *dev)>> static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, mtk_dp_resume);>> +static const struct mtk_dp_data mt8188_edp_data = {> +.bridge_type = DRM_MODE_CONNECTOR_eDP,> +.smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,> +.efuse_fmt = mt8195_edp_efuse_fmt,> +.audio_supported = false,> +.audio_pkt_in_hblank_area = false,> +.audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,> +};> +> +static const struct mtk_dp_data mt8188_dp_data = {> +.bridge_type = DRM_MODE_CONNECTOR_DisplayPort,> +.smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,> +.efuse_fmt = mt8195_dp_efuse_fmt,> +.audio_supported = true,> +.audio_pkt_in_hblank_area = true,> +.audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,> +};> +> static const struct mtk_dp_data mt8195_edp_data = {> .bridge_type = DRM_MODE_CONNECTOR_eDP,> .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,> .efuse_fmt = mt8195_edp_efuse_fmt,> .audio_supported = false,> +.audio_pkt_in_hblank_area = false,> +.audio_m_div2_bit = AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,> };>> static const struct mtk_dp_data mt8195_dp_data = {> @@ -2628,9 +2663,19 @@ static const struct mtk_dp_data mt8195_dp_data = {> .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,> .efuse_fmt = mt8195_dp_efuse_fmt,> .audio_supported = true,> +.audio_pkt_in_hblank_area = false,> +.audio_m_div2_bit = AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,> };>> static const struct of_device_id mtk_dp_of_match[] = {> +{> +.compatible = "mediatek,mt8188-edp-tx",> +.data = "">> +},> +{> +.compatible = "mediatek,mt8188-dp-tx",> +.data = "">> +},> {> .compatible = "mediatek,mt8195-edp-tx",> .data = "">> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h> index 84e38cef03c2..6d7f0405867e 100644> --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h> @@ -162,6 +162,7 @@> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2(1 << 8)> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4(2 << 8)> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8(3 << 8)> +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2(4 << 8)> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2(5 << 8)> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4(6 << 8)> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8(7 << 8)> @@ -228,6 +229,11 @@> VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 | \> SDP_DP13_EN_DP_ENC1_P0 | \> BS2BS_MODE_DP_ENC1_P0)> +> +#define MTK_DP_ENC1_P0_33740x3374> +#define SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASKBIT(12)> +#define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASKGENMASK(11, 0)> +> #define MTK_DP_ENC1_P0_33F40x33f4> #define DP_ENC_DUMMY_RW_1_AUDIO_RST_ENBIT(0)> #define DP_ENC_DUMMY_RW_1BIT(9) ************* MEDIATEK Confidentiality Notice ******************** The information contained in this e-mail message (including any attachments) may be confidential, proprietary, privileged, or otherwise exempt from disclosure under applicable laws. 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