From: Alex Deucher <alexander.deucher@xxxxxxx>
This is required for certain advanced functionality.
v2: save/restore list takes dword offsets
v3: rebase on gpu reset changes
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/radeon/clearstate_cayman.h | 1081 +++++++++++++++++++++++++
drivers/gpu/drm/radeon/clearstate_defs.h | 44 +
drivers/gpu/drm/radeon/clearstate_evergreen.h | 1080 ++++++++++++++++++++++++
drivers/gpu/drm/radeon/evergreen.c | 339 ++++++++
drivers/gpu/drm/radeon/evergreend.h | 19 +
drivers/gpu/drm/radeon/ni.c | 141 ++++-
drivers/gpu/drm/radeon/r600.c | 43 +-
drivers/gpu/drm/radeon/r600d.h | 4 -
drivers/gpu/drm/radeon/radeon.h | 13 +-
9 files changed, 2721 insertions(+), 43 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/clearstate_cayman.h
create mode 100644 drivers/gpu/drm/radeon/clearstate_defs.h
create mode 100644 drivers/gpu/drm/radeon/clearstate_evergreen.h
diff --git a/drivers/gpu/drm/radeon/clearstate_cayman.h b/drivers/gpu/drm/radeon/clearstate_cayman.h
new file mode 100644
index 0000000..c003394
--- /dev/null
+++ b/drivers/gpu/drm/radeon/clearstate_cayman.h
@@ -0,0 +1,1081 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+static const u32 SECT_CONTEXT_def_1[] =
+{
+ 0x00000000, // DB_RENDER_CONTROL
+ 0x00000000, // DB_COUNT_CONTROL
+ 0x00000000, // DB_DEPTH_VIEW
+ 0x00000000, // DB_RENDER_OVERRIDE
+ 0x00000000, // DB_RENDER_OVERRIDE2
+ 0x00000000, // DB_HTILE_DATA_BASE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // DB_STENCIL_CLEAR
+ 0x00000000, // DB_DEPTH_CLEAR
+ 0x00000000, // PA_SC_SCREEN_SCISSOR_TL
+ 0x40004000, // PA_SC_SCREEN_SCISSOR_BR
+ 0, // HOLE
+ 0x00000000, // DB_DEPTH_INFO
+ 0x00000000, // DB_Z_INFO
+ 0x00000000, // DB_STENCIL_INFO
+ 0x00000000, // DB_Z_READ_BASE
+ 0x00000000, // DB_STENCIL_READ_BASE
+ 0x00000000, // DB_Z_WRITE_BASE
+ 0x00000000, // DB_STENCIL_WRITE_BASE
+ 0x00000000, // DB_DEPTH_SIZE
+ 0x00000000, // DB_DEPTH_SLICE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_15
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_15
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_15
+ 0x00000000, // PA_SC_WINDOW_OFFSET
+ 0x80000000, // PA_SC_WINDOW_SCISSOR_TL
+ 0x40004000, // PA_SC_WINDOW_SCISSOR_BR
+ 0x0000ffff, // PA_SC_CLIPRECT_RULE
+ 0x00000000, // PA_SC_CLIPRECT_0_TL
+ 0x40004000, // PA_SC_CLIPRECT_0_BR
+ 0x00000000, // PA_SC_CLIPRECT_1_TL
+ 0x40004000, // PA_SC_CLIPRECT_1_BR
+ 0x00000000, // PA_SC_CLIPRECT_2_TL
+ 0x40004000, // PA_SC_CLIPRECT_2_BR
+ 0x00000000, // PA_SC_CLIPRECT_3_TL
+ 0x40004000, // PA_SC_CLIPRECT_3_BR
+ 0xaa99aaaa, // PA_SC_EDGERULE
+ 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET
+ 0xffffffff, // CB_TARGET_MASK
+ 0xffffffff, // CB_SHADER_MASK
+ 0x80000000, // PA_SC_GENERIC_SCISSOR_TL
+ 0x40004000, // PA_SC_GENERIC_SCISSOR_BR
+ 0x00000000, // COHER_DEST_BASE_0
+ 0x00000000, // COHER_DEST_BASE_1
+ 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR
+ 0x00000000, // PA_SC_VPORT_ZMIN_0
+ 0x3f800000, // PA_SC_VPORT_ZMAX_0
+ 0x00000000, // PA_SC_VPORT_ZMIN_1
+ 0x3f800000, // PA_SC_VPORT_ZMAX_1
+ 0x00000000, // PA_SC_VPORT_ZMIN_2
+ 0x3f800000, // PA_SC_VPORT_ZMAX_2
+ 0x00000000, // PA_SC_VPORT_ZMIN_3
+ 0x3f800000, // PA_SC_VPORT_ZMAX_3
+ 0x00000000, // PA_SC_VPORT_ZMIN_4
+ 0x3f800000, // PA_SC_VPORT_ZMAX_4
+ 0x00000000, // PA_SC_VPORT_ZMIN_5
+ 0x3f800000, // PA_SC_VPORT_ZMAX_5
+ 0x00000000, // PA_SC_VPORT_ZMIN_6
+ 0x3f800000, // PA_SC_VPORT_ZMAX_6
+ 0x00000000, // PA_SC_VPORT_ZMIN_7
+ 0x3f800000, // PA_SC_VPORT_ZMAX_7
+ 0x00000000, // PA_SC_VPORT_ZMIN_8
+ 0x3f800000, // PA_SC_VPORT_ZMAX_8
+ 0x00000000, // PA_SC_VPORT_ZMIN_9
+ 0x3f800000, // PA_SC_VPORT_ZMAX_9
+ 0x00000000, // PA_SC_VPORT_ZMIN_10
+ 0x3f800000, // PA_SC_VPORT_ZMAX_10
+ 0x00000000, // PA_SC_VPORT_ZMIN_11
+ 0x3f800000, // PA_SC_VPORT_ZMAX_11
+ 0x00000000, // PA_SC_VPORT_ZMIN_12
+ 0x3f800000, // PA_SC_VPORT_ZMAX_12
+ 0x00000000, // PA_SC_VPORT_ZMIN_13
+ 0x3f800000, // PA_SC_VPORT_ZMAX_13
+ 0x00000000, // PA_SC_VPORT_ZMIN_14
+ 0x3f800000, // PA_SC_VPORT_ZMAX_14
+ 0x00000000, // PA_SC_VPORT_ZMIN_15
+ 0x3f800000, // PA_SC_VPORT_ZMAX_15
+ 0x00000000, // SX_MISC
+ 0x00000000, // SX_SURFACE_SYNC
+ 0x00000000, // SX_SCATTER_EXPORT_BASE
+ 0x00000000, // SX_SCATTER_EXPORT_SIZE
+ 0x00000000, // CP_PERFMON_CNTX_CNTL
+ 0x00000000, // CP_RINGID
+ 0x00000000, // CP_VMID
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_VTX_SEMANTIC_0
+ 0x00000000, // SQ_VTX_SEMANTIC_1
+ 0x00000000, // SQ_VTX_SEMANTIC_2
+ 0x00000000, // SQ_VTX_SEMANTIC_3
+ 0x00000000, // SQ_VTX_SEMANTIC_4
+ 0x00000000, // SQ_VTX_SEMANTIC_5
+ 0x00000000, // SQ_VTX_SEMANTIC_6
+ 0x00000000, // SQ_VTX_SEMANTIC_7
+ 0x00000000, // SQ_VTX_SEMANTIC_8
+ 0x00000000, // SQ_VTX_SEMANTIC_9
+ 0x00000000, // SQ_VTX_SEMANTIC_10
+ 0x00000000, // SQ_VTX_SEMANTIC_11
+ 0x00000000, // SQ_VTX_SEMANTIC_12
+ 0x00000000, // SQ_VTX_SEMANTIC_13
+ 0x00000000, // SQ_VTX_SEMANTIC_14
+ 0x00000000, // SQ_VTX_SEMANTIC_15
+ 0x00000000, // SQ_VTX_SEMANTIC_16
+ 0x00000000, // SQ_VTX_SEMANTIC_17
+ 0x00000000, // SQ_VTX_SEMANTIC_18
+ 0x00000000, // SQ_VTX_SEMANTIC_19
+ 0x00000000, // SQ_VTX_SEMANTIC_20
+ 0x00000000, // SQ_VTX_SEMANTIC_21
+ 0x00000000, // SQ_VTX_SEMANTIC_22
+ 0x00000000, // SQ_VTX_SEMANTIC_23
+ 0x00000000, // SQ_VTX_SEMANTIC_24
+ 0x00000000, // SQ_VTX_SEMANTIC_25
+ 0x00000000, // SQ_VTX_SEMANTIC_26
+ 0x00000000, // SQ_VTX_SEMANTIC_27
+ 0x00000000, // SQ_VTX_SEMANTIC_28
+ 0x00000000, // SQ_VTX_SEMANTIC_29
+ 0x00000000, // SQ_VTX_SEMANTIC_30
+ 0x00000000, // SQ_VTX_SEMANTIC_31
+ 0xffffffff, // VGT_MAX_VTX_INDX
+ 0x00000000, // VGT_MIN_VTX_INDX
+ 0x00000000, // VGT_INDX_OFFSET
+ 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
+ 0x00000000, // SX_ALPHA_TEST_CONTROL
+ 0x00000000, // CB_BLEND_RED
+ 0x00000000, // CB_BLEND_GREEN
+ 0x00000000, // CB_BLEND_BLUE
+ 0x00000000, // CB_BLEND_ALPHA
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // DB_STENCILREFMASK
+ 0x00000000, // DB_STENCILREFMASK_BF
+ 0x00000000, // SX_ALPHA_REF
+ 0x00000000, // PA_CL_VPORT_XSCALE
+ 0x00000000, // PA_CL_VPORT_XOFFSET
+ 0x00000000, // PA_CL_VPORT_YSCALE
+ 0x00000000, // PA_CL_VPORT_YOFFSET
+ 0x00000000, // PA_CL_VPORT_ZSCALE
+ 0x00000000, // PA_CL_VPORT_ZOFFSET
+ 0x00000000, // PA_CL_VPORT_XSCALE_1
+ 0x00000000, // PA_CL_VPORT_XOFFSET_1
+ 0x00000000, // PA_CL_VPORT_YSCALE_1
+ 0x00000000, // PA_CL_VPORT_YOFFSET_1
+ 0x00000000, // PA_CL_VPORT_ZSCALE_1
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_1
+ 0x00000000, // PA_CL_VPORT_XSCALE_2
+ 0x00000000, // PA_CL_VPORT_XOFFSET_2
+ 0x00000000, // PA_CL_VPORT_YSCALE_2
+ 0x00000000, // PA_CL_VPORT_YOFFSET_2
+ 0x00000000, // PA_CL_VPORT_ZSCALE_2
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_2
+ 0x00000000, // PA_CL_VPORT_XSCALE_3
+ 0x00000000, // PA_CL_VPORT_XOFFSET_3
+ 0x00000000, // PA_CL_VPORT_YSCALE_3
+ 0x00000000, // PA_CL_VPORT_YOFFSET_3
+ 0x00000000, // PA_CL_VPORT_ZSCALE_3
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_3
+ 0x00000000, // PA_CL_VPORT_XSCALE_4
+ 0x00000000, // PA_CL_VPORT_XOFFSET_4
+ 0x00000000, // PA_CL_VPORT_YSCALE_4
+ 0x00000000, // PA_CL_VPORT_YOFFSET_4
+ 0x00000000, // PA_CL_VPORT_ZSCALE_4
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_4
+ 0x00000000, // PA_CL_VPORT_XSCALE_5
+ 0x00000000, // PA_CL_VPORT_XOFFSET_5
+ 0x00000000, // PA_CL_VPORT_YSCALE_5
+ 0x00000000, // PA_CL_VPORT_YOFFSET_5
+ 0x00000000, // PA_CL_VPORT_ZSCALE_5
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_5
+ 0x00000000, // PA_CL_VPORT_XSCALE_6
+ 0x00000000, // PA_CL_VPORT_XOFFSET_6
+ 0x00000000, // PA_CL_VPORT_YSCALE_6
+ 0x00000000, // PA_CL_VPORT_YOFFSET_6
+ 0x00000000, // PA_CL_VPORT_ZSCALE_6
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_6
+ 0x00000000, // PA_CL_VPORT_XSCALE_7
+ 0x00000000, // PA_CL_VPORT_XOFFSET_7
+ 0x00000000, // PA_CL_VPORT_YSCALE_7
+ 0x00000000, // PA_CL_VPORT_YOFFSET_7
+ 0x00000000, // PA_CL_VPORT_ZSCALE_7
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_7
+ 0x00000000, // PA_CL_VPORT_XSCALE_8
+ 0x00000000, // PA_CL_VPORT_XOFFSET_8
+ 0x00000000, // PA_CL_VPORT_YSCALE_8
+ 0x00000000, // PA_CL_VPORT_YOFFSET_8
+ 0x00000000, // PA_CL_VPORT_ZSCALE_8
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_8
+ 0x00000000, // PA_CL_VPORT_XSCALE_9
+ 0x00000000, // PA_CL_VPORT_XOFFSET_9
+ 0x00000000, // PA_CL_VPORT_YSCALE_9
+ 0x00000000, // PA_CL_VPORT_YOFFSET_9
+ 0x00000000, // PA_CL_VPORT_ZSCALE_9
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_9
+ 0x00000000, // PA_CL_VPORT_XSCALE_10
+ 0x00000000, // PA_CL_VPORT_XOFFSET_10
+ 0x00000000, // PA_CL_VPORT_YSCALE_10
+ 0x00000000, // PA_CL_VPORT_YOFFSET_10
+ 0x00000000, // PA_CL_VPORT_ZSCALE_10
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_10
+ 0x00000000, // PA_CL_VPORT_XSCALE_11
+ 0x00000000, // PA_CL_VPORT_XOFFSET_11
+ 0x00000000, // PA_CL_VPORT_YSCALE_11
+ 0x00000000, // PA_CL_VPORT_YOFFSET_11
+ 0x00000000, // PA_CL_VPORT_ZSCALE_11
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_11
+ 0x00000000, // PA_CL_VPORT_XSCALE_12
+ 0x00000000, // PA_CL_VPORT_XOFFSET_12
+ 0x00000000, // PA_CL_VPORT_YSCALE_12
+ 0x00000000, // PA_CL_VPORT_YOFFSET_12
+ 0x00000000, // PA_CL_VPORT_ZSCALE_12
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_12
+ 0x00000000, // PA_CL_VPORT_XSCALE_13
+ 0x00000000, // PA_CL_VPORT_XOFFSET_13
+ 0x00000000, // PA_CL_VPORT_YSCALE_13
+ 0x00000000, // PA_CL_VPORT_YOFFSET_13
+ 0x00000000, // PA_CL_VPORT_ZSCALE_13
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_13
+ 0x00000000, // PA_CL_VPORT_XSCALE_14
+ 0x00000000, // PA_CL_VPORT_XOFFSET_14
+ 0x00000000, // PA_CL_VPORT_YSCALE_14
+ 0x00000000, // PA_CL_VPORT_YOFFSET_14
+ 0x00000000, // PA_CL_VPORT_ZSCALE_14
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_14
+ 0x00000000, // PA_CL_VPORT_XSCALE_15
+ 0x00000000, // PA_CL_VPORT_XOFFSET_15
+ 0x00000000, // PA_CL_VPORT_YSCALE_15
+ 0x00000000, // PA_CL_VPORT_YOFFSET_15
+ 0x00000000, // PA_CL_VPORT_ZSCALE_15
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_15
+ 0x00000000, // PA_CL_UCP_0_X
+ 0x00000000, // PA_CL_UCP_0_Y
+ 0x00000000, // PA_CL_UCP_0_Z
+ 0x00000000, // PA_CL_UCP_0_W
+ 0x00000000, // PA_CL_UCP_1_X
+ 0x00000000, // PA_CL_UCP_1_Y
+ 0x00000000, // PA_CL_UCP_1_Z
+ 0x00000000, // PA_CL_UCP_1_W
+ 0x00000000, // PA_CL_UCP_2_X
+ 0x00000000, // PA_CL_UCP_2_Y
+ 0x00000000, // PA_CL_UCP_2_Z
+ 0x00000000, // PA_CL_UCP_2_W
+ 0x00000000, // PA_CL_UCP_3_X
+ 0x00000000, // PA_CL_UCP_3_Y
+ 0x00000000, // PA_CL_UCP_3_Z
+ 0x00000000, // PA_CL_UCP_3_W
+ 0x00000000, // PA_CL_UCP_4_X
+ 0x00000000, // PA_CL_UCP_4_Y
+ 0x00000000, // PA_CL_UCP_4_Z
+ 0x00000000, // PA_CL_UCP_4_W
+ 0x00000000, // PA_CL_UCP_5_X
+ 0x00000000, // PA_CL_UCP_5_Y
+ 0x00000000, // PA_CL_UCP_5_Z
+ 0x00000000, // PA_CL_UCP_5_W
+ 0x00000000, // SPI_VS_OUT_ID_0
+ 0x00000000, // SPI_VS_OUT_ID_1
+ 0x00000000, // SPI_VS_OUT_ID_2
+ 0x00000000, // SPI_VS_OUT_ID_3
+ 0x00000000, // SPI_VS_OUT_ID_4
+ 0x00000000, // SPI_VS_OUT_ID_5
+ 0x00000000, // SPI_VS_OUT_ID_6
+ 0x00000000, // SPI_VS_OUT_ID_7
+ 0x00000000, // SPI_VS_OUT_ID_8
+ 0x00000000, // SPI_VS_OUT_ID_9
+ 0x00000000, // SPI_PS_INPUT_CNTL_0
+ 0x00000000, // SPI_PS_INPUT_CNTL_1
+ 0x00000000, // SPI_PS_INPUT_CNTL_2
+ 0x00000000, // SPI_PS_INPUT_CNTL_3
+ 0x00000000, // SPI_PS_INPUT_CNTL_4
+ 0x00000000, // SPI_PS_INPUT_CNTL_5
+ 0x00000000, // SPI_PS_INPUT_CNTL_6
+ 0x00000000, // SPI_PS_INPUT_CNTL_7
+ 0x00000000, // SPI_PS_INPUT_CNTL_8
+ 0x00000000, // SPI_PS_INPUT_CNTL_9
+ 0x00000000, // SPI_PS_INPUT_CNTL_10
+ 0x00000000, // SPI_PS_INPUT_CNTL_11
+ 0x00000000, // SPI_PS_INPUT_CNTL_12
+ 0x00000000, // SPI_PS_INPUT_CNTL_13
+ 0x00000000, // SPI_PS_INPUT_CNTL_14
+ 0x00000000, // SPI_PS_INPUT_CNTL_15
+ 0x00000000, // SPI_PS_INPUT_CNTL_16
+ 0x00000000, // SPI_PS_INPUT_CNTL_17
+ 0x00000000, // SPI_PS_INPUT_CNTL_18
+ 0x00000000, // SPI_PS_INPUT_CNTL_19
+ 0x00000000, // SPI_PS_INPUT_CNTL_20
+ 0x00000000, // SPI_PS_INPUT_CNTL_21
+ 0x00000000, // SPI_PS_INPUT_CNTL_22
+ 0x00000000, // SPI_PS_INPUT_CNTL_23
+ 0x00000000, // SPI_PS_INPUT_CNTL_24
+ 0x00000000, // SPI_PS_INPUT_CNTL_25
+ 0x00000000, // SPI_PS_INPUT_CNTL_26
+ 0x00000000, // SPI_PS_INPUT_CNTL_27
+ 0x00000000, // SPI_PS_INPUT_CNTL_28
+ 0x00000000, // SPI_PS_INPUT_CNTL_29
+ 0x00000000, // SPI_PS_INPUT_CNTL_30
+ 0x00000000, // SPI_PS_INPUT_CNTL_31
+ 0x00000000, // SPI_VS_OUT_CONFIG
+ 0x00000001, // SPI_THREAD_GROUPING
+ 0x00000002, // SPI_PS_IN_CONTROL_0
+ 0x00000000, // SPI_PS_IN_CONTROL_1
+ 0x00000000, // SPI_INTERP_CONTROL_0
+ 0x00000000, // SPI_INPUT_Z
+ 0x00000000, // SPI_FOG_CNTL
+ 0x00000000, // SPI_BARYC_CNTL
+ 0x00000000, // SPI_PS_IN_CONTROL_2
+ 0x00000000, // SPI_COMPUTE_INPUT_CNTL
+ 0x00000000, // SPI_COMPUTE_NUM_THREAD_X
+ 0x00000000, // SPI_COMPUTE_NUM_THREAD_Y
+ 0x00000000, // SPI_COMPUTE_NUM_THREAD_Z
+ 0x00000000, // SPI_GPR_MGMT
+ 0x00000000, // SPI_LDS_MGMT
+ 0x00000000, // SPI_STACK_MGMT
+ 0x00000000, // SPI_WAVE_MGMT_1
+ 0x00000000, // SPI_WAVE_MGMT_2
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // GDS_ADDR_BASE
+ 0x00003fff, // GDS_ADDR_SIZE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // GDS_ORDERED_COUNT
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // GDS_APPEND_CONSUME_UAV0
+ 0x00000000, // GDS_APPEND_CONSUME_UAV1
+ 0x00000000, // GDS_APPEND_CONSUME_UAV2
+ 0x00000000, // GDS_APPEND_CONSUME_UAV3
+ 0x00000000, // GDS_APPEND_CONSUME_UAV4
+ 0x00000000, // GDS_APPEND_CONSUME_UAV5
+ 0x00000000, // GDS_APPEND_CONSUME_UAV6
+ 0x00000000, // GDS_APPEND_CONSUME_UAV7
+ 0x00000000, // GDS_APPEND_CONSUME_UAV8
+ 0x00000000, // GDS_APPEND_CONSUME_UAV9
+ 0x00000000, // GDS_APPEND_CONSUME_UAV10
+ 0x00000000, // GDS_APPEND_CONSUME_UAV11
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // CB_BLEND0_CONTROL
+ 0x00000000, // CB_BLEND1_CONTROL
+ 0x00000000, // CB_BLEND2_CONTROL
+ 0x00000000, // CB_BLEND3_CONTROL
+ 0x00000000, // CB_BLEND4_CONTROL
+ 0x00000000, // CB_BLEND5_CONTROL
+ 0x00000000, // CB_BLEND6_CONTROL
+ 0x00000000, // CB_BLEND7_CONTROL
+};
+static const u32 SECT_CONTEXT_def_2[] =
+{
+ 0x00000000, // PA_CL_POINT_X_RAD
+ 0x00000000, // PA_CL_POINT_Y_RAD
+ 0x00000000, // PA_CL_POINT_SIZE
+ 0x00000000, // PA_CL_POINT_CULL_RAD
+ 0x00000000, // VGT_DMA_BASE_HI
+ 0x00000000, // VGT_DMA_BASE
+};
+static const u32 SECT_CONTEXT_def_3[] =
+{
+ 0x00000000, // DB_DEPTH_CONTROL
+ 0x00000000, // DB_EQAA
+ 0x00000000, // CB_COLOR_CONTROL
+ 0x00000200, // DB_SHADER_CONTROL
+ 0x00000000, // PA_CL_CLIP_CNTL
+ 0x00000000, // PA_SU_SC_MODE_CNTL
+ 0x00000000, // PA_CL_VTE_CNTL
+ 0x00000000, // PA_CL_VS_OUT_CNTL
+ 0x00000000, // PA_CL_NANINF_CNTL
+ 0x00000000, // PA_SU_LINE_STIPPLE_CNTL
+ 0x00000000, // PA_SU_LINE_STIPPLE_SCALE
+ 0x00000000, // PA_SU_PRIM_FILTER_CNTL
+ 0x00000000, // SQ_LSTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_HSTMP_RING_ITEMSIZE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_PS
+ 0x00000000, // SQ_PGM_RESOURCES_PS
+ 0x00000000, // SQ_PGM_RESOURCES_2_PS
+ 0x00000000, // SQ_PGM_EXPORTS_PS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_VS
+ 0x00000000, // SQ_PGM_RESOURCES_VS
+ 0x00000000, // SQ_PGM_RESOURCES_2_VS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_GS
+ 0x00000000, // SQ_PGM_RESOURCES_GS
+ 0x00000000, // SQ_PGM_RESOURCES_2_GS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_ES
+ 0x00000000, // SQ_PGM_RESOURCES_ES
+ 0x00000000, // SQ_PGM_RESOURCES_2_ES
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_FS
+ 0x00000000, // SQ_PGM_RESOURCES_FS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_HS
+ 0x00000000, // SQ_PGM_RESOURCES_HS
+ 0x00000000, // SQ_PGM_RESOURCES_2_HS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_LS
+ 0x00000000, // SQ_PGM_RESOURCES_LS
+ 0x00000000, // SQ_PGM_RESOURCES_2_LS
+};
+static const u32 SECT_CONTEXT_def_4[] =
+{
+ 0x00000000, // SQ_LDS_ALLOC
+ 0x00000000, // SQ_LDS_ALLOC_PS
+ 0x00000000, // SQ_VTX_SEMANTIC_CLEAR
+ 0, // HOLE
+ 0x00000000, // SQ_THREAD_TRACE_CTRL
+ 0, // HOLE
+ 0x00000000, // SQ_ESGS_RING_ITEMSIZE
+ 0x00000000, // SQ_GSVS_RING_ITEMSIZE
+ 0x00000000, // SQ_ESTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_GSTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_VSTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_PSTMP_RING_ITEMSIZE
+ 0, // HOLE
+ 0x00000000, // SQ_GS_VERT_ITEMSIZE
+ 0x00000000, // SQ_GS_VERT_ITEMSIZE_1
+ 0x00000000, // SQ_GS_VERT_ITEMSIZE_2
+ 0x00000000, // SQ_GS_VERT_ITEMSIZE_3
+ 0x00000000, // SQ_GSVS_RING_OFFSET_1
+ 0x00000000, // SQ_GSVS_RING_OFFSET_2
+ 0x00000000, // SQ_GSVS_RING_OFFSET_3
+ 0x00000000, // SQ_GWS_RING_OFFSET
+ 0, // HOLE
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_15
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_15
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_15
+ 0x00000000, // PA_SU_POINT_SIZE
+ 0x00000000, // PA_SU_POINT_MINMAX
+ 0x00000000, // PA_SU_LINE_CNTL
+ 0x00000000, // PA_SC_LINE_STIPPLE
+ 0x00000000, // VGT_OUTPUT_PATH_CNTL
+ 0x00000000, // VGT_HOS_CNTL
+ 0x00000000, // VGT_HOS_MAX_TESS_LEVEL
+ 0x00000000, // VGT_HOS_MIN_TESS_LEVEL
+ 0x00000000, // VGT_HOS_REUSE_DEPTH
+ 0x00000000, // VGT_GROUP_PRIM_TYPE
+ 0x00000000, // VGT_GROUP_FIRST_DECR
+ 0x00000000, // VGT_GROUP_DECR
+ 0x00000000, // VGT_GROUP_VECT_0_CNTL
+ 0x00000000, // VGT_GROUP_VECT_1_CNTL
+ 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
+ 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
+ 0x00000000, // VGT_GS_MODE
+ 0, // HOLE
+ 0x00000000, // PA_SC_MODE_CNTL_0
+ 0x00000000, // PA_SC_MODE_CNTL_1
+ 0x00000000, // VGT_ENHANCE
+ 0x00000100, // VGT_GS_PER_ES
+ 0x00000080, // VGT_ES_PER_GS
+ 0x00000002, // VGT_GS_PER_VS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_GS_OUT_PRIM_TYPE
+ 0x00000000, // IA_ENHANCE
+};
+static const u32 SECT_CONTEXT_def_5[] =
+{
+ 0x00000000, // VGT_DMA_MAX_SIZE
+ 0x00000000, // VGT_DMA_INDEX_TYPE
+ 0, // HOLE
+ 0x00000000, // VGT_PRIMITIVEID_EN
+ 0x00000000, // VGT_DMA_NUM_INSTANCES
+};
+static const u32 SECT_CONTEXT_def_6[] =
+{
+ 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_INSTANCE_STEP_RATE_0
+ 0x00000000, // VGT_INSTANCE_STEP_RATE_1
+ 0x000000ff, // IA_MULTI_VGT_PARAM
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_REUSE_OFF
+ 0x00000000, // VGT_VTX_CNT_EN
+ 0x00000000, // DB_HTILE_SURFACE
+ 0x00000000, // DB_SRESULTS_COMPARE_STATE0
+ 0x00000000, // DB_SRESULTS_COMPARE_STATE1
+ 0x00000000, // DB_PRELOAD_CONTROL
+ 0, // HOLE
+ 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
+ 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
+ 0x00000000, // VGT_STRMOUT_BUFFER_BASE_0
+ 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
+ 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
+ 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
+ 0x00000000, // VGT_STRMOUT_BUFFER_BASE_1
+ 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
+ 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
+ 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
+ 0x00000000, // VGT_STRMOUT_BUFFER_BASE_2
+ 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
+ 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
+ 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
+ 0x00000000, // VGT_STRMOUT_BUFFER_BASE_3
+ 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_0
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_1
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_2
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_3
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET
+ 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
+ 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
+ 0, // HOLE
+ 0x00000000, // VGT_GS_MAX_VERT_OUT
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_0
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_1
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_2
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_3
+ 0x00000000, // VGT_SHADER_STAGES_EN
+ 0x00000000, // VGT_LS_HS_CONFIG
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_TF_PARAM
+ 0x00000000, // DB_ALPHA_TO_MASK
+};
+static const u32 SECT_CONTEXT_def_7[] =
+{
+ 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL
+ 0x00000000, // PA_SU_POLY_OFFSET_CLAMP
+ 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE
+ 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET
+ 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
+ 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
+ 0x00000000, // VGT_GS_INSTANCE_CNT
+ 0x00000000, // VGT_STRMOUT_CONFIG
+ 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
+ 0x00000000, // CB_IMMED0_BASE
+ 0x00000000, // CB_IMMED1_BASE
+ 0x00000000, // CB_IMMED2_BASE
+ 0x00000000, // CB_IMMED3_BASE
+ 0x00000000, // CB_IMMED4_BASE
+ 0x00000000, // CB_IMMED5_BASE
+ 0x00000000, // CB_IMMED6_BASE
+ 0x00000000, // CB_IMMED7_BASE
+ 0x00000000, // CB_IMMED8_BASE
+ 0x00000000, // CB_IMMED9_BASE
+ 0x00000000, // CB_IMMED10_BASE
+ 0x00000000, // CB_IMMED11_BASE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // PA_SC_CENTROID_PRIORITY_0
+ 0x00000000, // PA_SC_CENTROID_PRIORITY_1
+ 0x00001000, // PA_SC_LINE_CNTL
+ 0x00000000, // PA_SC_AA_CONFIG
+ 0x00000005, // PA_SU_VTX_CNTL
+ 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ
+ 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ
+ 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ
+ 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
+ 0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0
+ 0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1
+ 0x00000000, // CB_CLRCMP_CONTROL
+ 0x00000000, // CB_CLRCMP_SRC
+ 0x00000000, // CB_CLRCMP_DST
+ 0x00000000, // CB_CLRCMP_MSK
+ 0, // HOLE
+ 0, // HOLE
+ 0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL
+ 0x00000010, // VGT_OUT_DEALLOC_CNTL
+ 0x00000000, // CB_COLOR0_BASE
+ 0x00000000, // CB_COLOR0_PITCH
+ 0x00000000, // CB_COLOR0_SLICE
+ 0x00000000, // CB_COLOR0_VIEW
+ 0x00000000, // CB_COLOR0_INFO
+ 0x00000000, // CB_COLOR0_ATTRIB
+ 0x00000000, // CB_COLOR0_DIM
+ 0x00000000, // CB_COLOR0_CMASK
+ 0x00000000, // CB_COLOR0_CMASK_SLICE
+ 0x00000000, // CB_COLOR0_FMASK
+ 0x00000000, // CB_COLOR0_FMASK_SLICE
+ 0x00000000, // CB_COLOR0_CLEAR_WORD0
+ 0x00000000, // CB_COLOR0_CLEAR_WORD1
+ 0x00000000, // CB_COLOR0_CLEAR_WORD2
+ 0x00000000, // CB_COLOR0_CLEAR_WORD3
+ 0x00000000, // CB_COLOR1_BASE
+ 0x00000000, // CB_COLOR1_PITCH
+ 0x00000000, // CB_COLOR1_SLICE
+ 0x00000000, // CB_COLOR1_VIEW
+ 0x00000000, // CB_COLOR1_INFO
+ 0x00000000, // CB_COLOR1_ATTRIB
+ 0x00000000, // CB_COLOR1_DIM
+ 0x00000000, // CB_COLOR1_CMASK
+ 0x00000000, // CB_COLOR1_CMASK_SLICE
+ 0x00000000, // CB_COLOR1_FMASK
+ 0x00000000, // CB_COLOR1_FMASK_SLICE
+ 0x00000000, // CB_COLOR1_CLEAR_WORD0
+ 0x00000000, // CB_COLOR1_CLEAR_WORD1
+ 0x00000000, // CB_COLOR1_CLEAR_WORD2
+ 0x00000000, // CB_COLOR1_CLEAR_WORD3
+ 0x00000000, // CB_COLOR2_BASE
+ 0x00000000, // CB_COLOR2_PITCH
+ 0x00000000, // CB_COLOR2_SLICE
+ 0x00000000, // CB_COLOR2_VIEW
+ 0x00000000, // CB_COLOR2_INFO
+ 0x00000000, // CB_COLOR2_ATTRIB
+ 0x00000000, // CB_COLOR2_DIM
+ 0x00000000, // CB_COLOR2_CMASK
+ 0x00000000, // CB_COLOR2_CMASK_SLICE
+ 0x00000000, // CB_COLOR2_FMASK
+ 0x00000000, // CB_COLOR2_FMASK_SLICE
+ 0x00000000, // CB_COLOR2_CLEAR_WORD0
+ 0x00000000, // CB_COLOR2_CLEAR_WORD1
+ 0x00000000, // CB_COLOR2_CLEAR_WORD2
+ 0x00000000, // CB_COLOR2_CLEAR_WORD3
+ 0x00000000, // CB_COLOR3_BASE
+ 0x00000000, // CB_COLOR3_PITCH
+ 0x00000000, // CB_COLOR3_SLICE
+ 0x00000000, // CB_COLOR3_VIEW
+ 0x00000000, // CB_COLOR3_INFO
+ 0x00000000, // CB_COLOR3_ATTRIB
+ 0x00000000, // CB_COLOR3_DIM
+ 0x00000000, // CB_COLOR3_CMASK
+ 0x00000000, // CB_COLOR3_CMASK_SLICE
+ 0x00000000, // CB_COLOR3_FMASK
+ 0x00000000, // CB_COLOR3_FMASK_SLICE
+ 0x00000000, // CB_COLOR3_CLEAR_WORD0
+ 0x00000000, // CB_COLOR3_CLEAR_WORD1
+ 0x00000000, // CB_COLOR3_CLEAR_WORD2
+ 0x00000000, // CB_COLOR3_CLEAR_WORD3
+ 0x00000000, // CB_COLOR4_BASE
+ 0x00000000, // CB_COLOR4_PITCH
+ 0x00000000, // CB_COLOR4_SLICE
+ 0x00000000, // CB_COLOR4_VIEW
+ 0x00000000, // CB_COLOR4_INFO
+ 0x00000000, // CB_COLOR4_ATTRIB
+ 0x00000000, // CB_COLOR4_DIM
+ 0x00000000, // CB_COLOR4_CMASK
+ 0x00000000, // CB_COLOR4_CMASK_SLICE
+ 0x00000000, // CB_COLOR4_FMASK
+ 0x00000000, // CB_COLOR4_FMASK_SLICE
+ 0x00000000, // CB_COLOR4_CLEAR_WORD0
+ 0x00000000, // CB_COLOR4_CLEAR_WORD1
+ 0x00000000, // CB_COLOR4_CLEAR_WORD2
+ 0x00000000, // CB_COLOR4_CLEAR_WORD3
+ 0x00000000, // CB_COLOR5_BASE
+ 0x00000000, // CB_COLOR5_PITCH
+ 0x00000000, // CB_COLOR5_SLICE
+ 0x00000000, // CB_COLOR5_VIEW
+ 0x00000000, // CB_COLOR5_INFO
+ 0x00000000, // CB_COLOR5_ATTRIB
+ 0x00000000, // CB_COLOR5_DIM
+ 0x00000000, // CB_COLOR5_CMASK
+ 0x00000000, // CB_COLOR5_CMASK_SLICE
+ 0x00000000, // CB_COLOR5_FMASK
+ 0x00000000, // CB_COLOR5_FMASK_SLICE
+ 0x00000000, // CB_COLOR5_CLEAR_WORD0
+ 0x00000000, // CB_COLOR5_CLEAR_WORD1
+ 0x00000000, // CB_COLOR5_CLEAR_WORD2
+ 0x00000000, // CB_COLOR5_CLEAR_WORD3
+ 0x00000000, // CB_COLOR6_BASE
+ 0x00000000, // CB_COLOR6_PITCH
+ 0x00000000, // CB_COLOR6_SLICE
+ 0x00000000, // CB_COLOR6_VIEW
+ 0x00000000, // CB_COLOR6_INFO
+ 0x00000000, // CB_COLOR6_ATTRIB
+ 0x00000000, // CB_COLOR6_DIM
+ 0x00000000, // CB_COLOR6_CMASK
+ 0x00000000, // CB_COLOR6_CMASK_SLICE
+ 0x00000000, // CB_COLOR6_FMASK
+ 0x00000000, // CB_COLOR6_FMASK_SLICE
+ 0x00000000, // CB_COLOR6_CLEAR_WORD0
+ 0x00000000, // CB_COLOR6_CLEAR_WORD1
+ 0x00000000, // CB_COLOR6_CLEAR_WORD2
+ 0x00000000, // CB_COLOR6_CLEAR_WORD3
+ 0x00000000, // CB_COLOR7_BASE
+ 0x00000000, // CB_COLOR7_PITCH
+ 0x00000000, // CB_COLOR7_SLICE
+ 0x00000000, // CB_COLOR7_VIEW
+ 0x00000000, // CB_COLOR7_INFO
+ 0x00000000, // CB_COLOR7_ATTRIB
+ 0x00000000, // CB_COLOR7_DIM
+ 0x00000000, // CB_COLOR7_CMASK
+ 0x00000000, // CB_COLOR7_CMASK_SLICE
+ 0x00000000, // CB_COLOR7_FMASK
+ 0x00000000, // CB_COLOR7_FMASK_SLICE
+ 0x00000000, // CB_COLOR7_CLEAR_WORD0
+ 0x00000000, // CB_COLOR7_CLEAR_WORD1
+ 0x00000000, // CB_COLOR7_CLEAR_WORD2
+ 0x00000000, // CB_COLOR7_CLEAR_WORD3
+ 0x00000000, // CB_COLOR8_BASE
+ 0x00000000, // CB_COLOR8_PITCH
+ 0x00000000, // CB_COLOR8_SLICE
+ 0x00000000, // CB_COLOR8_VIEW
+ 0x00000000, // CB_COLOR8_INFO
+ 0x00000000, // CB_COLOR8_ATTRIB
+ 0x00000000, // CB_COLOR8_DIM
+ 0x00000000, // CB_COLOR9_BASE
+ 0x00000000, // CB_COLOR9_PITCH
+ 0x00000000, // CB_COLOR9_SLICE
+ 0x00000000, // CB_COLOR9_VIEW
+ 0x00000000, // CB_COLOR9_INFO
+ 0x00000000, // CB_COLOR9_ATTRIB
+ 0x00000000, // CB_COLOR9_DIM
+ 0x00000000, // CB_COLOR10_BASE
+ 0x00000000, // CB_COLOR10_PITCH
+ 0x00000000, // CB_COLOR10_SLICE
+ 0x00000000, // CB_COLOR10_VIEW
+ 0x00000000, // CB_COLOR10_INFO
+ 0x00000000, // CB_COLOR10_ATTRIB
+ 0x00000000, // CB_COLOR10_DIM
+ 0x00000000, // CB_COLOR11_BASE
+ 0x00000000, // CB_COLOR11_PITCH
+ 0x00000000, // CB_COLOR11_SLICE
+ 0x00000000, // CB_COLOR11_VIEW
+ 0x00000000, // CB_COLOR11_INFO
+ 0x00000000, // CB_COLOR11_ATTRIB
+ 0x00000000, // CB_COLOR11_DIM
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_15
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_15
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_15
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_15
+};
+static const struct cs_extent_def SECT_CONTEXT_defs[] =
+{
+ {SECT_CONTEXT_def_1, 0x0000a000, 488 },
+ {SECT_CONTEXT_def_2, 0x0000a1f5, 6 },
+ {SECT_CONTEXT_def_3, 0x0000a200, 55 },
+ {SECT_CONTEXT_def_4, 0x0000a23a, 99 },
+ {SECT_CONTEXT_def_5, 0x0000a29e, 5 },
+ {SECT_CONTEXT_def_6, 0x0000a2a5, 56 },
+ {SECT_CONTEXT_def_7, 0x0000a2de, 290 },
+ { 0, 0, 0 }
+};
+static const u32 SECT_CLEAR_def_1[] =
+{
+ 0xffffffff, // SQ_TEX_SAMPLER_CLEAR
+ 0xffffffff, // SQ_TEX_RESOURCE_CLEAR
+ 0xffffffff, // SQ_LOOP_BOOL_CLEAR
+};
+static const struct cs_extent_def SECT_CLEAR_defs[] =
+{
+ {SECT_CLEAR_def_1, 0x0000ffc0, 3 },
+ { 0, 0, 0 }
+};
+static const u32 SECT_CTRLCONST_def_1[] =
+{
+ 0x00000000, // SQ_VTX_BASE_VTX_LOC
+ 0x00000000, // SQ_VTX_START_INST_LOC
+};
+static const struct cs_extent_def SECT_CTRLCONST_defs[] =
+{
+ {SECT_CTRLCONST_def_1, 0x0000f3fc, 2 },
+ { 0, 0, 0 }
+};
+struct cs_section_def cayman_cs_data[] = {
+ { SECT_CONTEXT_defs, SECT_CONTEXT },
+ { SECT_CLEAR_defs, SECT_CLEAR },
+ { SECT_CTRLCONST_defs, SECT_CTRLCONST },
+ { 0, SECT_NONE }
+};
diff --git a/drivers/gpu/drm/radeon/clearstate_defs.h b/drivers/gpu/drm/radeon/clearstate_defs.h
new file mode 100644
index 0000000..3eda707
--- /dev/null
+++ b/drivers/gpu/drm/radeon/clearstate_defs.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef CLEARSTATE_DEFS_H
+#define CLEARSTATE_DEFS_H
+
+enum section_id {
+ SECT_NONE,
+ SECT_CONTEXT,
+ SECT_CLEAR,
+ SECT_CTRLCONST
+};
+
+struct cs_extent_def {
+ const unsigned int *extent;
+ const unsigned int reg_index;
+ const unsigned int reg_count;
+};
+
+struct cs_section_def {
+ const struct cs_extent_def *section;
+ const enum section_id id;
+};
+
+#endif
diff --git a/drivers/gpu/drm/radeon/clearstate_evergreen.h b/drivers/gpu/drm/radeon/clearstate_evergreen.h
new file mode 100644
index 0000000..4791d85
--- /dev/null
+++ b/drivers/gpu/drm/radeon/clearstate_evergreen.h
@@ -0,0 +1,1080 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+static const u32 SECT_CONTEXT_def_1[] =
+{
+ 0x00000000, // DB_RENDER_CONTROL
+ 0x00000000, // DB_COUNT_CONTROL
+ 0x00000000, // DB_DEPTH_VIEW
+ 0x00000000, // DB_RENDER_OVERRIDE
+ 0x00000000, // DB_RENDER_OVERRIDE2
+ 0x00000000, // DB_HTILE_DATA_BASE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // DB_STENCIL_CLEAR
+ 0x00000000, // DB_DEPTH_CLEAR
+ 0x00000000, // PA_SC_SCREEN_SCISSOR_TL
+ 0x40004000, // PA_SC_SCREEN_SCISSOR_BR
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // DB_Z_INFO
+ 0x00000000, // DB_STENCIL_INFO
+ 0x00000000, // DB_Z_READ_BASE
+ 0x00000000, // DB_STENCIL_READ_BASE
+ 0x00000000, // DB_Z_WRITE_BASE
+ 0x00000000, // DB_STENCIL_WRITE_BASE
+ 0x00000000, // DB_DEPTH_SIZE
+ 0x00000000, // DB_DEPTH_SLICE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_15
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_15
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_15
+ 0x00000000, // PA_SC_WINDOW_OFFSET
+ 0x80000000, // PA_SC_WINDOW_SCISSOR_TL
+ 0x40004000, // PA_SC_WINDOW_SCISSOR_BR
+ 0x0000ffff, // PA_SC_CLIPRECT_RULE
+ 0x00000000, // PA_SC_CLIPRECT_0_TL
+ 0x40004000, // PA_SC_CLIPRECT_0_BR
+ 0x00000000, // PA_SC_CLIPRECT_1_TL
+ 0x40004000, // PA_SC_CLIPRECT_1_BR
+ 0x00000000, // PA_SC_CLIPRECT_2_TL
+ 0x40004000, // PA_SC_CLIPRECT_2_BR
+ 0x00000000, // PA_SC_CLIPRECT_3_TL
+ 0x40004000, // PA_SC_CLIPRECT_3_BR
+ 0xaa99aaaa, // PA_SC_EDGERULE
+ 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET
+ 0xffffffff, // CB_TARGET_MASK
+ 0xffffffff, // CB_SHADER_MASK
+ 0x80000000, // PA_SC_GENERIC_SCISSOR_TL
+ 0x40004000, // PA_SC_GENERIC_SCISSOR_BR
+ 0x00000000, // COHER_DEST_BASE_0
+ 0x00000000, // COHER_DEST_BASE_1
+ 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR
+ 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL
+ 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR
+ 0x00000000, // PA_SC_VPORT_ZMIN_0
+ 0x3f800000, // PA_SC_VPORT_ZMAX_0
+ 0x00000000, // PA_SC_VPORT_ZMIN_1
+ 0x3f800000, // PA_SC_VPORT_ZMAX_1
+ 0x00000000, // PA_SC_VPORT_ZMIN_2
+ 0x3f800000, // PA_SC_VPORT_ZMAX_2
+ 0x00000000, // PA_SC_VPORT_ZMIN_3
+ 0x3f800000, // PA_SC_VPORT_ZMAX_3
+ 0x00000000, // PA_SC_VPORT_ZMIN_4
+ 0x3f800000, // PA_SC_VPORT_ZMAX_4
+ 0x00000000, // PA_SC_VPORT_ZMIN_5
+ 0x3f800000, // PA_SC_VPORT_ZMAX_5
+ 0x00000000, // PA_SC_VPORT_ZMIN_6
+ 0x3f800000, // PA_SC_VPORT_ZMAX_6
+ 0x00000000, // PA_SC_VPORT_ZMIN_7
+ 0x3f800000, // PA_SC_VPORT_ZMAX_7
+ 0x00000000, // PA_SC_VPORT_ZMIN_8
+ 0x3f800000, // PA_SC_VPORT_ZMAX_8
+ 0x00000000, // PA_SC_VPORT_ZMIN_9
+ 0x3f800000, // PA_SC_VPORT_ZMAX_9
+ 0x00000000, // PA_SC_VPORT_ZMIN_10
+ 0x3f800000, // PA_SC_VPORT_ZMAX_10
+ 0x00000000, // PA_SC_VPORT_ZMIN_11
+ 0x3f800000, // PA_SC_VPORT_ZMAX_11
+ 0x00000000, // PA_SC_VPORT_ZMIN_12
+ 0x3f800000, // PA_SC_VPORT_ZMAX_12
+ 0x00000000, // PA_SC_VPORT_ZMIN_13
+ 0x3f800000, // PA_SC_VPORT_ZMAX_13
+ 0x00000000, // PA_SC_VPORT_ZMIN_14
+ 0x3f800000, // PA_SC_VPORT_ZMAX_14
+ 0x00000000, // PA_SC_VPORT_ZMIN_15
+ 0x3f800000, // PA_SC_VPORT_ZMAX_15
+ 0x00000000, // SX_MISC
+ 0x00000000, // SX_SURFACE_SYNC
+ 0x00000000, // CP_PERFMON_CNTX_CNTL
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_VTX_SEMANTIC_0
+ 0x00000000, // SQ_VTX_SEMANTIC_1
+ 0x00000000, // SQ_VTX_SEMANTIC_2
+ 0x00000000, // SQ_VTX_SEMANTIC_3
+ 0x00000000, // SQ_VTX_SEMANTIC_4
+ 0x00000000, // SQ_VTX_SEMANTIC_5
+ 0x00000000, // SQ_VTX_SEMANTIC_6
+ 0x00000000, // SQ_VTX_SEMANTIC_7
+ 0x00000000, // SQ_VTX_SEMANTIC_8
+ 0x00000000, // SQ_VTX_SEMANTIC_9
+ 0x00000000, // SQ_VTX_SEMANTIC_10
+ 0x00000000, // SQ_VTX_SEMANTIC_11
+ 0x00000000, // SQ_VTX_SEMANTIC_12
+ 0x00000000, // SQ_VTX_SEMANTIC_13
+ 0x00000000, // SQ_VTX_SEMANTIC_14
+ 0x00000000, // SQ_VTX_SEMANTIC_15
+ 0x00000000, // SQ_VTX_SEMANTIC_16
+ 0x00000000, // SQ_VTX_SEMANTIC_17
+ 0x00000000, // SQ_VTX_SEMANTIC_18
+ 0x00000000, // SQ_VTX_SEMANTIC_19
+ 0x00000000, // SQ_VTX_SEMANTIC_20
+ 0x00000000, // SQ_VTX_SEMANTIC_21
+ 0x00000000, // SQ_VTX_SEMANTIC_22
+ 0x00000000, // SQ_VTX_SEMANTIC_23
+ 0x00000000, // SQ_VTX_SEMANTIC_24
+ 0x00000000, // SQ_VTX_SEMANTIC_25
+ 0x00000000, // SQ_VTX_SEMANTIC_26
+ 0x00000000, // SQ_VTX_SEMANTIC_27
+ 0x00000000, // SQ_VTX_SEMANTIC_28
+ 0x00000000, // SQ_VTX_SEMANTIC_29
+ 0x00000000, // SQ_VTX_SEMANTIC_30
+ 0x00000000, // SQ_VTX_SEMANTIC_31
+ 0xffffffff, // VGT_MAX_VTX_INDX
+ 0x00000000, // VGT_MIN_VTX_INDX
+ 0x00000000, // VGT_INDX_OFFSET
+ 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
+ 0x00000000, // SX_ALPHA_TEST_CONTROL
+ 0x00000000, // CB_BLEND_RED
+ 0x00000000, // CB_BLEND_GREEN
+ 0x00000000, // CB_BLEND_BLUE
+ 0x00000000, // CB_BLEND_ALPHA
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // DB_STENCILREFMASK
+ 0x00000000, // DB_STENCILREFMASK_BF
+ 0x00000000, // SX_ALPHA_REF
+ 0x00000000, // PA_CL_VPORT_XSCALE
+ 0x00000000, // PA_CL_VPORT_XOFFSET
+ 0x00000000, // PA_CL_VPORT_YSCALE
+ 0x00000000, // PA_CL_VPORT_YOFFSET
+ 0x00000000, // PA_CL_VPORT_ZSCALE
+ 0x00000000, // PA_CL_VPORT_ZOFFSET
+ 0x00000000, // PA_CL_VPORT_XSCALE_1
+ 0x00000000, // PA_CL_VPORT_XOFFSET_1
+ 0x00000000, // PA_CL_VPORT_YSCALE_1
+ 0x00000000, // PA_CL_VPORT_YOFFSET_1
+ 0x00000000, // PA_CL_VPORT_ZSCALE_1
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_1
+ 0x00000000, // PA_CL_VPORT_XSCALE_2
+ 0x00000000, // PA_CL_VPORT_XOFFSET_2
+ 0x00000000, // PA_CL_VPORT_YSCALE_2
+ 0x00000000, // PA_CL_VPORT_YOFFSET_2
+ 0x00000000, // PA_CL_VPORT_ZSCALE_2
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_2
+ 0x00000000, // PA_CL_VPORT_XSCALE_3
+ 0x00000000, // PA_CL_VPORT_XOFFSET_3
+ 0x00000000, // PA_CL_VPORT_YSCALE_3
+ 0x00000000, // PA_CL_VPORT_YOFFSET_3
+ 0x00000000, // PA_CL_VPORT_ZSCALE_3
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_3
+ 0x00000000, // PA_CL_VPORT_XSCALE_4
+ 0x00000000, // PA_CL_VPORT_XOFFSET_4
+ 0x00000000, // PA_CL_VPORT_YSCALE_4
+ 0x00000000, // PA_CL_VPORT_YOFFSET_4
+ 0x00000000, // PA_CL_VPORT_ZSCALE_4
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_4
+ 0x00000000, // PA_CL_VPORT_XSCALE_5
+ 0x00000000, // PA_CL_VPORT_XOFFSET_5
+ 0x00000000, // PA_CL_VPORT_YSCALE_5
+ 0x00000000, // PA_CL_VPORT_YOFFSET_5
+ 0x00000000, // PA_CL_VPORT_ZSCALE_5
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_5
+ 0x00000000, // PA_CL_VPORT_XSCALE_6
+ 0x00000000, // PA_CL_VPORT_XOFFSET_6
+ 0x00000000, // PA_CL_VPORT_YSCALE_6
+ 0x00000000, // PA_CL_VPORT_YOFFSET_6
+ 0x00000000, // PA_CL_VPORT_ZSCALE_6
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_6
+ 0x00000000, // PA_CL_VPORT_XSCALE_7
+ 0x00000000, // PA_CL_VPORT_XOFFSET_7
+ 0x00000000, // PA_CL_VPORT_YSCALE_7
+ 0x00000000, // PA_CL_VPORT_YOFFSET_7
+ 0x00000000, // PA_CL_VPORT_ZSCALE_7
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_7
+ 0x00000000, // PA_CL_VPORT_XSCALE_8
+ 0x00000000, // PA_CL_VPORT_XOFFSET_8
+ 0x00000000, // PA_CL_VPORT_YSCALE_8
+ 0x00000000, // PA_CL_VPORT_YOFFSET_8
+ 0x00000000, // PA_CL_VPORT_ZSCALE_8
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_8
+ 0x00000000, // PA_CL_VPORT_XSCALE_9
+ 0x00000000, // PA_CL_VPORT_XOFFSET_9
+ 0x00000000, // PA_CL_VPORT_YSCALE_9
+ 0x00000000, // PA_CL_VPORT_YOFFSET_9
+ 0x00000000, // PA_CL_VPORT_ZSCALE_9
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_9
+ 0x00000000, // PA_CL_VPORT_XSCALE_10
+ 0x00000000, // PA_CL_VPORT_XOFFSET_10
+ 0x00000000, // PA_CL_VPORT_YSCALE_10
+ 0x00000000, // PA_CL_VPORT_YOFFSET_10
+ 0x00000000, // PA_CL_VPORT_ZSCALE_10
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_10
+ 0x00000000, // PA_CL_VPORT_XSCALE_11
+ 0x00000000, // PA_CL_VPORT_XOFFSET_11
+ 0x00000000, // PA_CL_VPORT_YSCALE_11
+ 0x00000000, // PA_CL_VPORT_YOFFSET_11
+ 0x00000000, // PA_CL_VPORT_ZSCALE_11
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_11
+ 0x00000000, // PA_CL_VPORT_XSCALE_12
+ 0x00000000, // PA_CL_VPORT_XOFFSET_12
+ 0x00000000, // PA_CL_VPORT_YSCALE_12
+ 0x00000000, // PA_CL_VPORT_YOFFSET_12
+ 0x00000000, // PA_CL_VPORT_ZSCALE_12
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_12
+ 0x00000000, // PA_CL_VPORT_XSCALE_13
+ 0x00000000, // PA_CL_VPORT_XOFFSET_13
+ 0x00000000, // PA_CL_VPORT_YSCALE_13
+ 0x00000000, // PA_CL_VPORT_YOFFSET_13
+ 0x00000000, // PA_CL_VPORT_ZSCALE_13
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_13
+ 0x00000000, // PA_CL_VPORT_XSCALE_14
+ 0x00000000, // PA_CL_VPORT_XOFFSET_14
+ 0x00000000, // PA_CL_VPORT_YSCALE_14
+ 0x00000000, // PA_CL_VPORT_YOFFSET_14
+ 0x00000000, // PA_CL_VPORT_ZSCALE_14
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_14
+ 0x00000000, // PA_CL_VPORT_XSCALE_15
+ 0x00000000, // PA_CL_VPORT_XOFFSET_15
+ 0x00000000, // PA_CL_VPORT_YSCALE_15
+ 0x00000000, // PA_CL_VPORT_YOFFSET_15
+ 0x00000000, // PA_CL_VPORT_ZSCALE_15
+ 0x00000000, // PA_CL_VPORT_ZOFFSET_15
+ 0x00000000, // PA_CL_UCP_0_X
+ 0x00000000, // PA_CL_UCP_0_Y
+ 0x00000000, // PA_CL_UCP_0_Z
+ 0x00000000, // PA_CL_UCP_0_W
+ 0x00000000, // PA_CL_UCP_1_X
+ 0x00000000, // PA_CL_UCP_1_Y
+ 0x00000000, // PA_CL_UCP_1_Z
+ 0x00000000, // PA_CL_UCP_1_W
+ 0x00000000, // PA_CL_UCP_2_X
+ 0x00000000, // PA_CL_UCP_2_Y
+ 0x00000000, // PA_CL_UCP_2_Z
+ 0x00000000, // PA_CL_UCP_2_W
+ 0x00000000, // PA_CL_UCP_3_X
+ 0x00000000, // PA_CL_UCP_3_Y
+ 0x00000000, // PA_CL_UCP_3_Z
+ 0x00000000, // PA_CL_UCP_3_W
+ 0x00000000, // PA_CL_UCP_4_X
+ 0x00000000, // PA_CL_UCP_4_Y
+ 0x00000000, // PA_CL_UCP_4_Z
+ 0x00000000, // PA_CL_UCP_4_W
+ 0x00000000, // PA_CL_UCP_5_X
+ 0x00000000, // PA_CL_UCP_5_Y
+ 0x00000000, // PA_CL_UCP_5_Z
+ 0x00000000, // PA_CL_UCP_5_W
+ 0x00000000, // SPI_VS_OUT_ID_0
+ 0x00000000, // SPI_VS_OUT_ID_1
+ 0x00000000, // SPI_VS_OUT_ID_2
+ 0x00000000, // SPI_VS_OUT_ID_3
+ 0x00000000, // SPI_VS_OUT_ID_4
+ 0x00000000, // SPI_VS_OUT_ID_5
+ 0x00000000, // SPI_VS_OUT_ID_6
+ 0x00000000, // SPI_VS_OUT_ID_7
+ 0x00000000, // SPI_VS_OUT_ID_8
+ 0x00000000, // SPI_VS_OUT_ID_9
+ 0x00000000, // SPI_PS_INPUT_CNTL_0
+ 0x00000000, // SPI_PS_INPUT_CNTL_1
+ 0x00000000, // SPI_PS_INPUT_CNTL_2
+ 0x00000000, // SPI_PS_INPUT_CNTL_3
+ 0x00000000, // SPI_PS_INPUT_CNTL_4
+ 0x00000000, // SPI_PS_INPUT_CNTL_5
+ 0x00000000, // SPI_PS_INPUT_CNTL_6
+ 0x00000000, // SPI_PS_INPUT_CNTL_7
+ 0x00000000, // SPI_PS_INPUT_CNTL_8
+ 0x00000000, // SPI_PS_INPUT_CNTL_9
+ 0x00000000, // SPI_PS_INPUT_CNTL_10
+ 0x00000000, // SPI_PS_INPUT_CNTL_11
+ 0x00000000, // SPI_PS_INPUT_CNTL_12
+ 0x00000000, // SPI_PS_INPUT_CNTL_13
+ 0x00000000, // SPI_PS_INPUT_CNTL_14
+ 0x00000000, // SPI_PS_INPUT_CNTL_15
+ 0x00000000, // SPI_PS_INPUT_CNTL_16
+ 0x00000000, // SPI_PS_INPUT_CNTL_17
+ 0x00000000, // SPI_PS_INPUT_CNTL_18
+ 0x00000000, // SPI_PS_INPUT_CNTL_19
+ 0x00000000, // SPI_PS_INPUT_CNTL_20
+ 0x00000000, // SPI_PS_INPUT_CNTL_21
+ 0x00000000, // SPI_PS_INPUT_CNTL_22
+ 0x00000000, // SPI_PS_INPUT_CNTL_23
+ 0x00000000, // SPI_PS_INPUT_CNTL_24
+ 0x00000000, // SPI_PS_INPUT_CNTL_25
+ 0x00000000, // SPI_PS_INPUT_CNTL_26
+ 0x00000000, // SPI_PS_INPUT_CNTL_27
+ 0x00000000, // SPI_PS_INPUT_CNTL_28
+ 0x00000000, // SPI_PS_INPUT_CNTL_29
+ 0x00000000, // SPI_PS_INPUT_CNTL_30
+ 0x00000000, // SPI_PS_INPUT_CNTL_31
+ 0x00000000, // SPI_VS_OUT_CONFIG
+ 0x00000001, // SPI_THREAD_GROUPING
+ 0x00000000, // SPI_PS_IN_CONTROL_0
+ 0x00000000, // SPI_PS_IN_CONTROL_1
+ 0x00000000, // SPI_INTERP_CONTROL_0
+ 0x00000000, // SPI_INPUT_Z
+ 0x00000000, // SPI_FOG_CNTL
+ 0x00000000, // SPI_BARYC_CNTL
+ 0x00000000, // SPI_PS_IN_CONTROL_2
+ 0x00000000, // SPI_COMPUTE_INPUT_CNTL
+ 0x00000000, // SPI_COMPUTE_NUM_THREAD_X
+ 0x00000000, // SPI_COMPUTE_NUM_THREAD_Y
+ 0x00000000, // SPI_COMPUTE_NUM_THREAD_Z
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // GDS_ADDR_BASE
+ 0x00003fff, // GDS_ADDR_SIZE
+ 0x00000001, // GDS_ORDERED_WAVE_PER_SE
+ 0x00000000, // GDS_APPEND_CONSUME_UAV0
+ 0x00000000, // GDS_APPEND_CONSUME_UAV1
+ 0x00000000, // GDS_APPEND_CONSUME_UAV2
+ 0x00000000, // GDS_APPEND_CONSUME_UAV3
+ 0x00000000, // GDS_APPEND_CONSUME_UAV4
+ 0x00000000, // GDS_APPEND_CONSUME_UAV5
+ 0x00000000, // GDS_APPEND_CONSUME_UAV6
+ 0x00000000, // GDS_APPEND_CONSUME_UAV7
+ 0x00000000, // GDS_APPEND_CONSUME_UAV8
+ 0x00000000, // GDS_APPEND_CONSUME_UAV9
+ 0x00000000, // GDS_APPEND_CONSUME_UAV10
+ 0x00000000, // GDS_APPEND_CONSUME_UAV11
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // CB_BLEND0_CONTROL
+ 0x00000000, // CB_BLEND1_CONTROL
+ 0x00000000, // CB_BLEND2_CONTROL
+ 0x00000000, // CB_BLEND3_CONTROL
+ 0x00000000, // CB_BLEND4_CONTROL
+ 0x00000000, // CB_BLEND5_CONTROL
+ 0x00000000, // CB_BLEND6_CONTROL
+ 0x00000000, // CB_BLEND7_CONTROL
+};
+static const u32 SECT_CONTEXT_def_2[] =
+{
+ 0x00000000, // PA_CL_POINT_X_RAD
+ 0x00000000, // PA_CL_POINT_Y_RAD
+ 0x00000000, // PA_CL_POINT_SIZE
+ 0x00000000, // PA_CL_POINT_CULL_RAD
+ 0x00000000, // VGT_DMA_BASE_HI
+ 0x00000000, // VGT_DMA_BASE
+};
+static const u32 SECT_CONTEXT_def_3[] =
+{
+ 0x00000000, // DB_DEPTH_CONTROL
+ 0, // HOLE
+ 0x00000000, // CB_COLOR_CONTROL
+ 0x00000200, // DB_SHADER_CONTROL
+ 0x00000000, // PA_CL_CLIP_CNTL
+ 0x00000000, // PA_SU_SC_MODE_CNTL
+ 0x00000000, // PA_CL_VTE_CNTL
+ 0x00000000, // PA_CL_VS_OUT_CNTL
+ 0x00000000, // PA_CL_NANINF_CNTL
+ 0x00000000, // PA_SU_LINE_STIPPLE_CNTL
+ 0x00000000, // PA_SU_LINE_STIPPLE_SCALE
+ 0x00000000, // PA_SU_PRIM_FILTER_CNTL
+ 0x00000000, // SQ_LSTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_HSTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_DYN_GPR_RESOURCE_LIMIT_1
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_PS
+ 0x00000000, // SQ_PGM_RESOURCES_PS
+ 0x00000000, // SQ_PGM_RESOURCES_2_PS
+ 0x00000000, // SQ_PGM_EXPORTS_PS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_VS
+ 0x00000000, // SQ_PGM_RESOURCES_VS
+ 0x00000000, // SQ_PGM_RESOURCES_2_VS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_GS
+ 0x00000000, // SQ_PGM_RESOURCES_GS
+ 0x00000000, // SQ_PGM_RESOURCES_2_GS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_ES
+ 0x00000000, // SQ_PGM_RESOURCES_ES
+ 0x00000000, // SQ_PGM_RESOURCES_2_ES
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_FS
+ 0x00000000, // SQ_PGM_RESOURCES_FS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_HS
+ 0x00000000, // SQ_PGM_RESOURCES_HS
+ 0x00000000, // SQ_PGM_RESOURCES_2_HS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_PGM_START_LS
+ 0x00000000, // SQ_PGM_RESOURCES_LS
+ 0x00000000, // SQ_PGM_RESOURCES_2_LS
+};
+static const u32 SECT_CONTEXT_def_4[] =
+{
+ 0x00000000, // SQ_LDS_ALLOC
+ 0x00000000, // SQ_LDS_ALLOC_PS
+ 0x00000000, // SQ_VTX_SEMANTIC_CLEAR
+ 0, // HOLE
+ 0x00000000, // SQ_THREAD_TRACE_CTRL
+ 0, // HOLE
+ 0x00000000, // SQ_ESGS_RING_ITEMSIZE
+ 0x00000000, // SQ_GSVS_RING_ITEMSIZE
+ 0x00000000, // SQ_ESTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_GSTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_VSTMP_RING_ITEMSIZE
+ 0x00000000, // SQ_PSTMP_RING_ITEMSIZE
+ 0, // HOLE
+ 0x00000000, // SQ_GS_VERT_ITEMSIZE
+ 0x00000000, // SQ_GS_VERT_ITEMSIZE_1
+ 0x00000000, // SQ_GS_VERT_ITEMSIZE_2
+ 0x00000000, // SQ_GS_VERT_ITEMSIZE_3
+ 0x00000000, // SQ_GSVS_RING_OFFSET_1
+ 0x00000000, // SQ_GSVS_RING_OFFSET_2
+ 0x00000000, // SQ_GSVS_RING_OFFSET_3
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_PS_15
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_VS_15
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_GS_15
+ 0x00000000, // PA_SU_POINT_SIZE
+ 0x00000000, // PA_SU_POINT_MINMAX
+ 0x00000000, // PA_SU_LINE_CNTL
+ 0x00000000, // PA_SC_LINE_STIPPLE
+ 0x00000000, // VGT_OUTPUT_PATH_CNTL
+ 0x00000000, // VGT_HOS_CNTL
+ 0x00000000, // VGT_HOS_MAX_TESS_LEVEL
+ 0x00000000, // VGT_HOS_MIN_TESS_LEVEL
+ 0x00000000, // VGT_HOS_REUSE_DEPTH
+ 0x00000000, // VGT_GROUP_PRIM_TYPE
+ 0x00000000, // VGT_GROUP_FIRST_DECR
+ 0x00000000, // VGT_GROUP_DECR
+ 0x00000000, // VGT_GROUP_VECT_0_CNTL
+ 0x00000000, // VGT_GROUP_VECT_1_CNTL
+ 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
+ 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
+ 0x00000000, // VGT_GS_MODE
+ 0, // HOLE
+ 0x00000000, // PA_SC_MODE_CNTL_0
+ 0x00000000, // PA_SC_MODE_CNTL_1
+ 0x00000000, // VGT_ENHANCE
+ 0x00000000, // VGT_GS_PER_ES
+ 0x00000000, // VGT_ES_PER_GS
+ 0x00000000, // VGT_GS_PER_VS
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_GS_OUT_PRIM_TYPE
+};
+static const u32 SECT_CONTEXT_def_5[] =
+{
+ 0x00000000, // VGT_DMA_MAX_SIZE
+ 0x00000000, // VGT_DMA_INDEX_TYPE
+ 0, // HOLE
+ 0x00000000, // VGT_PRIMITIVEID_EN
+ 0x00000000, // VGT_DMA_NUM_INSTANCES
+};
+static const u32 SECT_CONTEXT_def_6[] =
+{
+ 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_INSTANCE_STEP_RATE_0
+ 0x00000000, // VGT_INSTANCE_STEP_RATE_1
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_REUSE_OFF
+ 0x00000000, // VGT_VTX_CNT_EN
+ 0x00000000, // DB_HTILE_SURFACE
+ 0x00000000, // DB_SRESULTS_COMPARE_STATE0
+ 0x00000000, // DB_SRESULTS_COMPARE_STATE1
+ 0x00000000, // DB_PRELOAD_CONTROL
+ 0, // HOLE
+ 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
+ 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
+ 0x00000000, // VGT_STRMOUT_BUFFER_BASE_0
+ 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
+ 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
+ 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
+ 0x00000000, // VGT_STRMOUT_BUFFER_BASE_1
+ 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
+ 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
+ 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
+ 0x00000000, // VGT_STRMOUT_BUFFER_BASE_2
+ 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
+ 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
+ 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
+ 0x00000000, // VGT_STRMOUT_BUFFER_BASE_3
+ 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_0
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_1
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_2
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_3
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET
+ 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
+ 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
+ 0, // HOLE
+ 0x00000000, // VGT_GS_MAX_VERT_OUT
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_0
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_1
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_2
+ 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_3
+ 0x00000000, // VGT_SHADER_STAGES_EN
+ 0x00000000, // VGT_LS_HS_CONFIG
+ 0x00000000, // VGT_LS_SIZE
+ 0x00000000, // VGT_HS_SIZE
+ 0x00000000, // VGT_LS_HS_ALLOC
+ 0x00000000, // VGT_HS_PATCH_CONST
+ 0x00000000, // VGT_TF_PARAM
+ 0x00000000, // DB_ALPHA_TO_MASK
+};
+static const u32 SECT_CONTEXT_def_7[] =
+{
+ 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL
+ 0x00000000, // PA_SU_POLY_OFFSET_CLAMP
+ 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE
+ 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET
+ 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
+ 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
+ 0x00000000, // VGT_GS_INSTANCE_CNT
+ 0x00000000, // VGT_STRMOUT_CONFIG
+ 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
+ 0x00000000, // CB_IMMED0_BASE
+ 0x00000000, // CB_IMMED1_BASE
+ 0x00000000, // CB_IMMED2_BASE
+ 0x00000000, // CB_IMMED3_BASE
+ 0x00000000, // CB_IMMED4_BASE
+ 0x00000000, // CB_IMMED5_BASE
+ 0x00000000, // CB_IMMED6_BASE
+ 0x00000000, // CB_IMMED7_BASE
+ 0x00000000, // CB_IMMED8_BASE
+ 0x00000000, // CB_IMMED9_BASE
+ 0x00000000, // CB_IMMED10_BASE
+ 0x00000000, // CB_IMMED11_BASE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00001000, // PA_SC_LINE_CNTL
+ 0x00000000, // PA_SC_AA_CONFIG
+ 0x00000005, // PA_SU_VTX_CNTL
+ 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ
+ 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ
+ 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ
+ 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_0
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_1
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_2
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_3
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_4
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_5
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_6
+ 0x00000000, // PA_SC_AA_SAMPLE_LOCS_7
+ 0xffffffff, // PA_SC_AA_MASK
+ 0x00000000, // CB_CLRCMP_CONTROL
+ 0x00000000, // CB_CLRCMP_SRC
+ 0x00000000, // CB_CLRCMP_DST
+ 0x00000000, // CB_CLRCMP_MSK
+ 0, // HOLE
+ 0, // HOLE
+ 0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL
+ 0x00000010, // VGT_OUT_DEALLOC_CNTL
+ 0x00000000, // CB_COLOR0_BASE
+ 0x00000000, // CB_COLOR0_PITCH
+ 0x00000000, // CB_COLOR0_SLICE
+ 0x00000000, // CB_COLOR0_VIEW
+ 0x00000000, // CB_COLOR0_INFO
+ 0x00000000, // CB_COLOR0_ATTRIB
+ 0x00000000, // CB_COLOR0_DIM
+ 0x00000000, // CB_COLOR0_CMASK
+ 0x00000000, // CB_COLOR0_CMASK_SLICE
+ 0x00000000, // CB_COLOR0_FMASK
+ 0x00000000, // CB_COLOR0_FMASK_SLICE
+ 0x00000000, // CB_COLOR0_CLEAR_WORD0
+ 0x00000000, // CB_COLOR0_CLEAR_WORD1
+ 0x00000000, // CB_COLOR0_CLEAR_WORD2
+ 0x00000000, // CB_COLOR0_CLEAR_WORD3
+ 0x00000000, // CB_COLOR1_BASE
+ 0x00000000, // CB_COLOR1_PITCH
+ 0x00000000, // CB_COLOR1_SLICE
+ 0x00000000, // CB_COLOR1_VIEW
+ 0x00000000, // CB_COLOR1_INFO
+ 0x00000000, // CB_COLOR1_ATTRIB
+ 0x00000000, // CB_COLOR1_DIM
+ 0x00000000, // CB_COLOR1_CMASK
+ 0x00000000, // CB_COLOR1_CMASK_SLICE
+ 0x00000000, // CB_COLOR1_FMASK
+ 0x00000000, // CB_COLOR1_FMASK_SLICE
+ 0x00000000, // CB_COLOR1_CLEAR_WORD0
+ 0x00000000, // CB_COLOR1_CLEAR_WORD1
+ 0x00000000, // CB_COLOR1_CLEAR_WORD2
+ 0x00000000, // CB_COLOR1_CLEAR_WORD3
+ 0x00000000, // CB_COLOR2_BASE
+ 0x00000000, // CB_COLOR2_PITCH
+ 0x00000000, // CB_COLOR2_SLICE
+ 0x00000000, // CB_COLOR2_VIEW
+ 0x00000000, // CB_COLOR2_INFO
+ 0x00000000, // CB_COLOR2_ATTRIB
+ 0x00000000, // CB_COLOR2_DIM
+ 0x00000000, // CB_COLOR2_CMASK
+ 0x00000000, // CB_COLOR2_CMASK_SLICE
+ 0x00000000, // CB_COLOR2_FMASK
+ 0x00000000, // CB_COLOR2_FMASK_SLICE
+ 0x00000000, // CB_COLOR2_CLEAR_WORD0
+ 0x00000000, // CB_COLOR2_CLEAR_WORD1
+ 0x00000000, // CB_COLOR2_CLEAR_WORD2
+ 0x00000000, // CB_COLOR2_CLEAR_WORD3
+ 0x00000000, // CB_COLOR3_BASE
+ 0x00000000, // CB_COLOR3_PITCH
+ 0x00000000, // CB_COLOR3_SLICE
+ 0x00000000, // CB_COLOR3_VIEW
+ 0x00000000, // CB_COLOR3_INFO
+ 0x00000000, // CB_COLOR3_ATTRIB
+ 0x00000000, // CB_COLOR3_DIM
+ 0x00000000, // CB_COLOR3_CMASK
+ 0x00000000, // CB_COLOR3_CMASK_SLICE
+ 0x00000000, // CB_COLOR3_FMASK
+ 0x00000000, // CB_COLOR3_FMASK_SLICE
+ 0x00000000, // CB_COLOR3_CLEAR_WORD0
+ 0x00000000, // CB_COLOR3_CLEAR_WORD1
+ 0x00000000, // CB_COLOR3_CLEAR_WORD2
+ 0x00000000, // CB_COLOR3_CLEAR_WORD3
+ 0x00000000, // CB_COLOR4_BASE
+ 0x00000000, // CB_COLOR4_PITCH
+ 0x00000000, // CB_COLOR4_SLICE
+ 0x00000000, // CB_COLOR4_VIEW
+ 0x00000000, // CB_COLOR4_INFO
+ 0x00000000, // CB_COLOR4_ATTRIB
+ 0x00000000, // CB_COLOR4_DIM
+ 0x00000000, // CB_COLOR4_CMASK
+ 0x00000000, // CB_COLOR4_CMASK_SLICE
+ 0x00000000, // CB_COLOR4_FMASK
+ 0x00000000, // CB_COLOR4_FMASK_SLICE
+ 0x00000000, // CB_COLOR4_CLEAR_WORD0
+ 0x00000000, // CB_COLOR4_CLEAR_WORD1
+ 0x00000000, // CB_COLOR4_CLEAR_WORD2
+ 0x00000000, // CB_COLOR4_CLEAR_WORD3
+ 0x00000000, // CB_COLOR5_BASE
+ 0x00000000, // CB_COLOR5_PITCH
+ 0x00000000, // CB_COLOR5_SLICE
+ 0x00000000, // CB_COLOR5_VIEW
+ 0x00000000, // CB_COLOR5_INFO
+ 0x00000000, // CB_COLOR5_ATTRIB
+ 0x00000000, // CB_COLOR5_DIM
+ 0x00000000, // CB_COLOR5_CMASK
+ 0x00000000, // CB_COLOR5_CMASK_SLICE
+ 0x00000000, // CB_COLOR5_FMASK
+ 0x00000000, // CB_COLOR5_FMASK_SLICE
+ 0x00000000, // CB_COLOR5_CLEAR_WORD0
+ 0x00000000, // CB_COLOR5_CLEAR_WORD1
+ 0x00000000, // CB_COLOR5_CLEAR_WORD2
+ 0x00000000, // CB_COLOR5_CLEAR_WORD3
+ 0x00000000, // CB_COLOR6_BASE
+ 0x00000000, // CB_COLOR6_PITCH
+ 0x00000000, // CB_COLOR6_SLICE
+ 0x00000000, // CB_COLOR6_VIEW
+ 0x00000000, // CB_COLOR6_INFO
+ 0x00000000, // CB_COLOR6_ATTRIB
+ 0x00000000, // CB_COLOR6_DIM
+ 0x00000000, // CB_COLOR6_CMASK
+ 0x00000000, // CB_COLOR6_CMASK_SLICE
+ 0x00000000, // CB_COLOR6_FMASK
+ 0x00000000, // CB_COLOR6_FMASK_SLICE
+ 0x00000000, // CB_COLOR6_CLEAR_WORD0
+ 0x00000000, // CB_COLOR6_CLEAR_WORD1
+ 0x00000000, // CB_COLOR6_CLEAR_WORD2
+ 0x00000000, // CB_COLOR6_CLEAR_WORD3
+ 0x00000000, // CB_COLOR7_BASE
+ 0x00000000, // CB_COLOR7_PITCH
+ 0x00000000, // CB_COLOR7_SLICE
+ 0x00000000, // CB_COLOR7_VIEW
+ 0x00000000, // CB_COLOR7_INFO
+ 0x00000000, // CB_COLOR7_ATTRIB
+ 0x00000000, // CB_COLOR7_DIM
+ 0x00000000, // CB_COLOR7_CMASK
+ 0x00000000, // CB_COLOR7_CMASK_SLICE
+ 0x00000000, // CB_COLOR7_FMASK
+ 0x00000000, // CB_COLOR7_FMASK_SLICE
+ 0x00000000, // CB_COLOR7_CLEAR_WORD0
+ 0x00000000, // CB_COLOR7_CLEAR_WORD1
+ 0x00000000, // CB_COLOR7_CLEAR_WORD2
+ 0x00000000, // CB_COLOR7_CLEAR_WORD3
+ 0x00000000, // CB_COLOR8_BASE
+ 0x00000000, // CB_COLOR8_PITCH
+ 0x00000000, // CB_COLOR8_SLICE
+ 0x00000000, // CB_COLOR8_VIEW
+ 0x00000000, // CB_COLOR8_INFO
+ 0x00000000, // CB_COLOR8_ATTRIB
+ 0x00000000, // CB_COLOR8_DIM
+ 0x00000000, // CB_COLOR9_BASE
+ 0x00000000, // CB_COLOR9_PITCH
+ 0x00000000, // CB_COLOR9_SLICE
+ 0x00000000, // CB_COLOR9_VIEW
+ 0x00000000, // CB_COLOR9_INFO
+ 0x00000000, // CB_COLOR9_ATTRIB
+ 0x00000000, // CB_COLOR9_DIM
+ 0x00000000, // CB_COLOR10_BASE
+ 0x00000000, // CB_COLOR10_PITCH
+ 0x00000000, // CB_COLOR10_SLICE
+ 0x00000000, // CB_COLOR10_VIEW
+ 0x00000000, // CB_COLOR10_INFO
+ 0x00000000, // CB_COLOR10_ATTRIB
+ 0x00000000, // CB_COLOR10_DIM
+ 0x00000000, // CB_COLOR11_BASE
+ 0x00000000, // CB_COLOR11_PITCH
+ 0x00000000, // CB_COLOR11_SLICE
+ 0x00000000, // CB_COLOR11_VIEW
+ 0x00000000, // CB_COLOR11_INFO
+ 0x00000000, // CB_COLOR11_ATTRIB
+ 0x00000000, // CB_COLOR11_DIM
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0, // HOLE
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_HS_15
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_0
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_1
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_2
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_3
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_4
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_5
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_6
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_7
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_8
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_9
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_10
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_11
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_12
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_13
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_14
+ 0x00000000, // SQ_ALU_CONST_CACHE_LS_15
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_15
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_0
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_1
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_2
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_3
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_4
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_5
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_6
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_7
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_8
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_9
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_10
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_11
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_12
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_13
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_14
+ 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_15
+};
+static const struct cs_extent_def SECT_CONTEXT_defs[] =
+{
+ {SECT_CONTEXT_def_1, 0x0000a000, 488 },
+ {SECT_CONTEXT_def_2, 0x0000a1f5, 6 },
+ {SECT_CONTEXT_def_3, 0x0000a200, 55 },
+ {SECT_CONTEXT_def_4, 0x0000a23a, 98 },
+ {SECT_CONTEXT_def_5, 0x0000a29e, 5 },
+ {SECT_CONTEXT_def_6, 0x0000a2a5, 56 },
+ {SECT_CONTEXT_def_7, 0x0000a2de, 290 },
+ { 0, 0, 0 }
+};
+static const u32 SECT_CLEAR_def_1[] =
+{
+ 0xffffffff, // SQ_TEX_SAMPLER_CLEAR
+ 0xffffffff, // SQ_TEX_RESOURCE_CLEAR
+ 0xffffffff, // SQ_LOOP_BOOL_CLEAR
+};
+static const struct cs_extent_def SECT_CLEAR_defs[] =
+{
+ {SECT_CLEAR_def_1, 0x0000ffc0, 3 },
+ { 0, 0, 0 }
+};
+static const u32 SECT_CTRLCONST_def_1[] =
+{
+ 0x00000000, // SQ_VTX_BASE_VTX_LOC
+ 0x00000000, // SQ_VTX_START_INST_LOC
+};
+static const struct cs_extent_def SECT_CTRLCONST_defs[] =
+{
+ {SECT_CTRLCONST_def_1, 0x0000f3fc, 2 },
+ { 0, 0, 0 }
+};
+struct cs_section_def evergreen_cs_data[] = {
+ { SECT_CONTEXT_defs, SECT_CONTEXT },
+ { SECT_CLEAR_defs, SECT_CLEAR },
+ { SECT_CTRLCONST_defs, SECT_CTRLCONST },
+ { 0, SECT_NONE }
+};
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 6b559cb5..b9f64f0 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -45,6 +45,94 @@ static const u32 crtc_offsets[6] =
EVERGREEN_CRTC5_REGISTER_OFFSET
};
+#include "clearstate_evergreen.h"
+
+static u32 sumo_rlc_save_restore_register_list[] =
+{
+ 0x98fc,
+ 0x9830,
+ 0x9834,
+ 0x9838,
+ 0x9870,
+ 0x9874,
+ 0x8a14,
+ 0x8b24,
+ 0x8bcc,
+ 0x8b10,
+ 0x8d00,
+ 0x8d04,
+ 0x8c00,
+ 0x8c04,
+ 0x8c08,
+ 0x8c0c,
+ 0x8d8c,
+ 0x8c20,
+ 0x8c24,
+ 0x8c28,
+ 0x8c18,
+ 0x8c1c,
+ 0x8cf0,
+ 0x8e2c,
+ 0x8e38,
+ 0x8c30,
+ 0x9508,
+ 0x9688,
+ 0x9608,
+ 0x960c,
+ 0x9610,
+ 0x9614,
+ 0x88c4,
+ 0x88d4,
+ 0xa008,
+ 0x900c,
+ 0x9100,
+ 0x913c,
+ 0x98f8,
+ 0x98f4,
+ 0x9b7c,
+ 0x3f8c,
+ 0x8950,
+ 0x8954,
+ 0x8a18,
+ 0x8b28,
+ 0x9144,
+ 0x9148,
+ 0x914c,
+ 0x3f90,
+ 0x3f94,
+ 0x915c,
+ 0x9160,
+ 0x9178,
+ 0x917c,
+ 0x9180,
+ 0x918c,
+ 0x9190,
+ 0x9194,
+ 0x9198,
+ 0x919c,
+ 0x91a8,
+ 0x91ac,
+ 0x91b0,
+ 0x91b4,
+ 0x91b8,
+ 0x91c4,
+ 0x91c8,
+ 0x91cc,
+ 0x91d0,
+ 0x91d4,
+ 0x91e0,
+ 0x91e4,
+ 0x91ec,
+ 0x91f0,
+ 0x91f4,
+ 0x9200,
+ 0x9204,
+ 0x929c,
+ 0x9150,
+ 0x802c,
+};
+static u32 sumo_rlc_save_restore_register_list_size = ARRAY_SIZE(sumo_rlc_save_restore_register_list);
+
static void evergreen_gpu_init(struct radeon_device *rdev);
void evergreen_fini(struct radeon_device *rdev);
void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
@@ -3723,6 +3811,241 @@ bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
return radeon_ring_test_lockup(rdev, ring);
}
+/*
+ * RLC
+ */
+#define RLC_SAVE_RESTORE_LIST_END_MARKER 0x00000000
+#define RLC_CLEAR_STATE_END_MARKER 0x00000001
+
+void sumo_rlc_fini(struct radeon_device *rdev)
+{
+ int r;
+
+ /* save restore block */
+ if (rdev->rlc.save_restore_obj) {
+ r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
+ if (unlikely(r != 0))
+ dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
+ radeon_bo_unpin(rdev->rlc.save_restore_obj);
+ radeon_bo_unreserve(rdev->rlc.save_restore_obj);
+
+ radeon_bo_unref(&rdev->rlc.save_restore_obj);
+ rdev->rlc.save_restore_obj = NULL;
+ }
+
+ /* clear state block */
+ if (rdev->rlc.clear_state_obj) {
+ r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
+ if (unlikely(r != 0))
+ dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
+ radeon_bo_unpin(rdev->rlc.clear_state_obj);
+ radeon_bo_unreserve(rdev->rlc.clear_state_obj);
+
+ radeon_bo_unref(&rdev->rlc.clear_state_obj);
+ rdev->rlc.clear_state_obj = NULL;
+ }
+}
+
+int sumo_rlc_init(struct radeon_device *rdev)
+{
+ u32 *src_ptr;
+ volatile u32 *dst_ptr;
+ u32 dws, data, i, j, k, reg_num;
+ u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index;
+ u64 reg_list_mc_addr;
+ struct cs_section_def *cs_data;
+ int r;
+
+ src_ptr = rdev->rlc.reg_list;
+ dws = rdev->rlc.reg_list_size;
+ cs_data = rdev->rlc.cs_data;
+
+ /* save restore block */
+ if (rdev->rlc.save_restore_obj == NULL) {
+ r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
+ RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.save_restore_obj);
+ if (r) {
+ dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
+ return r;
+ }
+ }
+
+ r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
+ if (unlikely(r != 0)) {
+ sumo_rlc_fini(rdev);
+ return r;
+ }
+ r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
+ &rdev->rlc.save_restore_gpu_addr);
+ if (r) {
+ radeon_bo_unreserve(rdev->rlc.save_restore_obj);
+ dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
+ sumo_rlc_fini(rdev);
+ return r;
+ }
+ r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
+ if (r) {
+ dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
+ sumo_rlc_fini(rdev);
+ return r;
+ }
+ /* write the sr buffer */
+ dst_ptr = rdev->rlc.sr_ptr;
+ /* format:
+ * dw0: (reg2 << 16) | reg1
+ * dw1: reg1 save space
+ * dw2: reg2 save space
+ */
+ for (i = 0; i < dws; i++) {
+ data = src_ptr[i] >> 2;
+ i++;
+ if (i < dws)
+ data |= (src_ptr[i] >> 2) << 16;
+ j = (((i - 1) * 3) / 2);
+ dst_ptr[j] = data;
+ }
+ j = ((i * 3) / 2);
+ dst_ptr[j] = RLC_SAVE_RESTORE_LIST_END_MARKER;
+
+ radeon_bo_kunmap(rdev->rlc.save_restore_obj);
+ radeon_bo_unreserve(rdev->rlc.save_restore_obj);
+
+ /* clear state block */
+ reg_list_num = 0;
+ dws = 0;
+ for (i = 0; cs_data[i].section != NULL; i++) {
+ for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
+ reg_list_num++;
+ dws += cs_data[i].section[j].reg_count;
+ }
+ }
+ reg_list_blk_index = (3 * reg_list_num + 2);
+ dws += reg_list_blk_index;
+
+ if (rdev->rlc.clear_state_obj == NULL) {
+ r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
+ RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
+ if (r) {
+ dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
+ sumo_rlc_fini(rdev);
+ return r;
+ }
+ }
+ r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
+ if (unlikely(r != 0)) {
+ sumo_rlc_fini(rdev);
+ return r;
+ }
+ r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
+ &rdev->rlc.clear_state_gpu_addr);
+ if (r) {
+
+ radeon_bo_unreserve(rdev->rlc.clear_state_obj);
+ dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
+ sumo_rlc_fini(rdev);
+ return r;
+ }
+ r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
+ if (r) {
+ dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
+ sumo_rlc_fini(rdev);
+ return r;
+ }
+ /* set up the cs buffer */
+ dst_ptr = rdev->rlc.cs_ptr;
+ reg_list_hdr_blk_index = 0;
+ reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
+ data = upper_32_bits(reg_list_mc_addr);
+ dst_ptr[reg_list_hdr_blk_index] = data;
+ reg_list_hdr_blk_index++;
+ for (i = 0; cs_data[i].section != NULL; i++) {
+ for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
+ reg_num = cs_data[i].section[j].reg_count;
+ data = reg_list_mc_addr & 0xffffffff;
+ dst_ptr[reg_list_hdr_blk_index] = data;
+ reg_list_hdr_blk_index++;
+
+ data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
+ dst_ptr[reg_list_hdr_blk_index] = data;
+ reg_list_hdr_blk_index++;
+
+ data = 0x08000000 | (reg_num * 4);
+ dst_ptr[reg_list_hdr_blk_index] = data;
+ reg_list_hdr_blk_index++;
+
+ for (k = 0; k < reg_num; k++) {
+ data = cs_data[i].section[j].extent[k];
+ dst_ptr[reg_list_blk_index + k] = data;
+ }
+ reg_list_mc_addr += reg_num * 4;
+ reg_list_blk_index += reg_num;
+ }
+ }
+ dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
+
+ radeon_bo_kunmap(rdev->rlc.clear_state_obj);
+ radeon_bo_unreserve(rdev->rlc.clear_state_obj);
+
+ return 0;
+}
+
+static void evergreen_rlc_start(struct radeon_device *rdev)
+{
+ if (rdev->flags & RADEON_IS_IGP)
+ WREG32(RLC_CNTL, RLC_ENABLE | GFX_POWER_GATING_ENABLE | GFX_POWER_GATING_SRC);
+ else
+ WREG32(RLC_CNTL, RLC_ENABLE);
+}
+
+int evergreen_rlc_resume(struct radeon_device *rdev)
+{
+ u32 i;
+ const __be32 *fw_data;
+
+ if (!rdev->rlc_fw)
+ return -EINVAL;
+
+ r600_rlc_stop(rdev);
+
+ WREG32(RLC_HB_CNTL, 0);
+
+ if (rdev->flags & RADEON_IS_IGP) {
+ WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
+ WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
+ } else {
+ WREG32(RLC_HB_BASE, 0);
+ WREG32(RLC_HB_RPTR, 0);
+ WREG32(RLC_HB_WPTR, 0);
+ }
+ WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
+ WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
+ WREG32(RLC_MC_CNTL, 0);
+ WREG32(RLC_UCODE_CNTL, 0);
+
+ fw_data = (const __be32 *)rdev->rlc_fw->data;
+ if (rdev->family >= CHIP_ARUBA) {
+ for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
+ WREG32(RLC_UCODE_ADDR, i);
+ WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
+ }
+ } else if (rdev->family >= CHIP_CAYMAN) {
+ for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
+ WREG32(RLC_UCODE_ADDR, i);
+ WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
+ }
+ } else {
+ for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
+ WREG32(RLC_UCODE_ADDR, i);
+ WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
+ }
+ }
+ WREG32(RLC_UCODE_ADDR, 0);
+
+ evergreen_rlc_start(rdev);
+
+ return 0;
+}
+
/* Interrupts */
u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
@@ -4721,6 +5044,18 @@ static int evergreen_startup(struct radeon_device *rdev)
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
}
+ /* allocate rlc buffers */
+ if (rdev->flags & RADEON_IS_IGP) {
+ rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
+ rdev->rlc.reg_list_size = sumo_rlc_save_restore_register_list_size;
+ rdev->rlc.cs_data = evergreen_cs_data;
+ r = sumo_rlc_init(rdev);
+ if (r) {
+ DRM_ERROR("Failed to init rlc BOs!\n");
+ return r;
+ }
+ }
+
/* allocate wb buffer */
r = radeon_wb_init(rdev);
if (r)
@@ -4952,6 +5287,8 @@ int evergreen_init(struct radeon_device *rdev)
r700_cp_fini(rdev);
r600_dma_fini(rdev);
r600_irq_fini(rdev);
+ if (rdev->flags & RADEON_IS_IGP)
+ sumo_rlc_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
radeon_irq_kms_fini(rdev);
@@ -4980,6 +5317,8 @@ void evergreen_fini(struct radeon_device *rdev)
r700_cp_fini(rdev);
r600_dma_fini(rdev);
r600_irq_fini(rdev);
+ if (rdev->flags & RADEON_IS_IGP)
+ sumo_rlc_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
radeon_irq_kms_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 75c0563..8603b7c 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -90,6 +90,25 @@
#define CG_VCLK_STATUS 0x61c
#define CG_SCRATCH1 0x820
+#define RLC_CNTL 0x3f00
+# define RLC_ENABLE (1 << 0)
+# define GFX_POWER_GATING_ENABLE (1 << 7)
+# define GFX_POWER_GATING_SRC (1 << 8)
+#define RLC_HB_BASE 0x3f10
+#define RLC_HB_CNTL 0x3f0c
+#define RLC_HB_RPTR 0x3f20
+#define RLC_HB_WPTR 0x3f1c
+#define RLC_HB_WPTR_LSB_ADDR 0x3f14
+#define RLC_HB_WPTR_MSB_ADDR 0x3f18
+#define RLC_MC_CNTL 0x3f44
+#define RLC_UCODE_CNTL 0x3f48
+#define RLC_UCODE_ADDR 0x3f2c
+#define RLC_UCODE_DATA 0x3f30
+
+/* new for TN */
+#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
+#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
+
#define GRBM_GFX_INDEX 0x802C
#define INSTANCE_INDEX(x) ((x) << 0)
#define SE_INDEX(x) ((x) << 16)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 9284346..c73d713 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -34,6 +34,134 @@
#include "ni_reg.h"
#include "cayman_blit_shaders.h"
#include "radeon_ucode.h"
+#include "clearstate_cayman.h"
+
+static u32 tn_rlc_save_restore_register_list[] =
+{
+ 0x98fc,
+ 0x98f0,
+ 0x9834,
+ 0x9838,
+ 0x9870,
+ 0x9874,
+ 0x8a14,
+ 0x8b24,
+ 0x8bcc,
+ 0x8b10,
+ 0x8c30,
+ 0x8d00,
+ 0x8d04,
+ 0x8c00,
+ 0x8c04,
+ 0x8c10,
+ 0x8c14,
+ 0x8d8c,
+ 0x8cf0,
+ 0x8e38,
+ 0x9508,
+ 0x9688,
+ 0x9608,
+ 0x960c,
+ 0x9610,
+ 0x9614,
+ 0x88c4,
+ 0x8978,
+ 0x88d4,
+ 0x900c,
+ 0x9100,
+ 0x913c,
+ 0x90e8,
+ 0x9354,
+ 0xa008,
+ 0x98f8,
+ 0x9148,
+ 0x914c,
+ 0x3f94,
+ 0x98f4,
+ 0x9b7c,
+ 0x3f8c,
+ 0x8950,
+ 0x8954,
+ 0x8a18,
+ 0x8b28,
+ 0x9144,
+ 0x3f90,
+ 0x915c,
+ 0x9160,
+ 0x9178,
+ 0x917c,
+ 0x9180,
+ 0x918c,
+ 0x9190,
+ 0x9194,
+ 0x9198,
+ 0x919c,
+ 0x91a8,
+ 0x91ac,
+ 0x91b0,
+ 0x91b4,
+ 0x91b8,
+ 0x91c4,
+ 0x91c8,
+ 0x91cc,
+ 0x91d0,
+ 0x91d4,
+ 0x91e0,
+ 0x91e4,
+ 0x91ec,
+ 0x91f0,
+ 0x91f4,
+ 0x9200,
+ 0x9204,
+ 0x929c,
+ 0x8030,
+ 0x9150,
+ 0x9a60,
+ 0x920c,
+ 0x9210,
+ 0x9228,
+ 0x922c,
+ 0x9244,
+ 0x9248,
+ 0x91e8,
+ 0x9294,
+ 0x9208,
+ 0x9224,
+ 0x9240,
+ 0x9220,
+ 0x923c,
+ 0x9258,
+ 0x9744,
+ 0xa200,
+ 0xa204,
+ 0xa208,
+ 0xa20c,
+ 0x8d58,
+ 0x9030,
+ 0x9034,
+ 0x9038,
+ 0x903c,
+ 0x9040,
+ 0x9654,
+ 0x897c,
+ 0xa210,
+ 0xa214,
+ 0x9868,
+ 0xa02c,
+ 0x9664,
+ 0x9698,
+ 0x949c,
+ 0x8e10,
+ 0x8e18,
+ 0x8c50,
+ 0x8c58,
+ 0x8c60,
+ 0x8c68,
+ 0x89b4,
+ 0x9830,
+ 0x802c,
+};
+static u32 tn_rlc_save_restore_register_list_size = ARRAY_SIZE(tn_rlc_save_restore_register_list);
extern bool evergreen_is_display_hung(struct radeon_device *rdev);
extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
@@ -45,8 +173,8 @@ extern void evergreen_irq_suspend(struct radeon_device *rdev);
extern int evergreen_mc_init(struct radeon_device *rdev);
extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
-extern void si_rlc_fini(struct radeon_device *rdev);
-extern int si_rlc_init(struct radeon_device *rdev);
+extern void sumo_rlc_fini(struct radeon_device *rdev);
+extern int sumo_rlc_init(struct radeon_device *rdev);
/* Firmware Names */
MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
@@ -1969,7 +2097,10 @@ static int cayman_startup(struct radeon_device *rdev)
/* allocate rlc buffers */
if (rdev->flags & RADEON_IS_IGP) {
- r = si_rlc_init(rdev);
+ rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
+ rdev->rlc.reg_list_size = tn_rlc_save_restore_register_list_size;
+ rdev->rlc.cs_data = cayman_cs_data;
+ r = sumo_rlc_init(rdev);
if (r) {
DRM_ERROR("Failed to init rlc BOs!\n");
return r;
@@ -2226,7 +2357,7 @@ int cayman_init(struct radeon_device *rdev)
cayman_dma_fini(rdev);
r600_irq_fini(rdev);
if (rdev->flags & RADEON_IS_IGP)
- si_rlc_fini(rdev);
+ sumo_rlc_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
radeon_vm_manager_fini(rdev);
@@ -2257,7 +2388,7 @@ void cayman_fini(struct radeon_device *rdev)
cayman_dma_fini(rdev);
r600_irq_fini(rdev);
if (rdev->flags & RADEON_IS_IGP)
- si_rlc_fini(rdev);
+ sumo_rlc_fini(rdev);
radeon_wb_fini(rdev);
radeon_vm_manager_fini(rdev);
radeon_ib_pool_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6089261..4678ed1 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -97,6 +97,7 @@ static void r600_gpu_init(struct radeon_device *rdev);
void r600_fini(struct radeon_device *rdev);
void r600_irq_disable(struct radeon_device *rdev);
static void r600_pcie_gen2_enable(struct radeon_device *rdev);
+extern int evergreen_rlc_resume(struct radeon_device *rdev);
/**
* r600_get_xclk - get the xclk
@@ -3778,7 +3779,7 @@ static void r600_rlc_start(struct radeon_device *rdev)
WREG32(RLC_CNTL, RLC_ENABLE);
}
-static int r600_rlc_init(struct radeon_device *rdev)
+static int r600_rlc_resume(struct radeon_device *rdev)
{
u32 i;
const __be32 *fw_data;
@@ -3790,39 +3791,16 @@ static int r600_rlc_init(struct radeon_device *rdev)
WREG32(RLC_HB_CNTL, 0);
- if (rdev->family == CHIP_ARUBA) {
- WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
- WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
- }
- if (rdev->family <= CHIP_CAYMAN) {
- WREG32(RLC_HB_BASE, 0);
- WREG32(RLC_HB_RPTR, 0);
- WREG32(RLC_HB_WPTR, 0);
- }
- if (rdev->family <= CHIP_CAICOS) {
- WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
- WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
- }
+ WREG32(RLC_HB_BASE, 0);
+ WREG32(RLC_HB_RPTR, 0);
+ WREG32(RLC_HB_WPTR, 0);
+ WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
+ WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
WREG32(RLC_MC_CNTL, 0);
WREG32(RLC_UCODE_CNTL, 0);
fw_data = (const __be32 *)rdev->rlc_fw->data;
- if (rdev->family >= CHIP_ARUBA) {
- for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
- WREG32(RLC_UCODE_ADDR, i);
- WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
- }
- } else if (rdev->family >= CHIP_CAYMAN) {
- for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
- WREG32(RLC_UCODE_ADDR, i);
- WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
- }
- } else if (rdev->family >= CHIP_CEDAR) {
- for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
- WREG32(RLC_UCODE_ADDR, i);
- WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
- }
- } else if (rdev->family >= CHIP_RV770) {
+ if (rdev->family >= CHIP_RV770) {
for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
WREG32(RLC_UCODE_ADDR, i);
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
@@ -3936,7 +3914,10 @@ int r600_irq_init(struct radeon_device *rdev)
r600_disable_interrupts(rdev);
/* init rlc */
- ret = r600_rlc_init(rdev);
+ if (rdev->family >= CHIP_CEDAR)
+ ret = evergreen_rlc_resume(rdev);
+ else
+ ret = r600_rlc_resume(rdev);
if (ret) {
r600_ih_ring_fini(rdev);
return ret;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 79df558..a3f926c 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -684,10 +684,6 @@
#define RLC_UCODE_ADDR 0x3f2c
#define RLC_UCODE_DATA 0x3f30
-/* new for TN */
-#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
-#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
-
#define SRBM_SOFT_RESET 0xe60
# define SOFT_RESET_DMA (1 << 12)
# define SOFT_RESET_RLC (1 << 13)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 40053c8..f4cb768 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -826,15 +826,22 @@ struct r600_blit {
};
/*
- * SI RLC stuff
+ * RLC stuff
*/
-struct si_rlc {
+#include "clearstate_defs.h"
+
+struct radeon_rlc {
/* for power gating */
struct radeon_bo *save_restore_obj;
uint64_t save_restore_gpu_addr;
+ volatile uint32_t *sr_ptr;
+ u32 *reg_list;
+ u32 reg_list_size;
/* for clear state */
struct radeon_bo *clear_state_obj;
uint64_t clear_state_gpu_addr;
+ volatile uint32_t *cs_ptr;
+ struct cs_section_def *cs_data;
};
int radeon_ib_get(struct radeon_device *rdev, int ring,
@@ -1774,7 +1781,7 @@ struct radeon_device {
struct r600_vram_scratch vram_scratch;
int msi_enabled; /* msi enabled */
struct r600_ih ih; /* r6/700 interrupt ring */
- struct si_rlc rlc;
+ struct radeon_rlc rlc;
struct radeon_mec mec;
struct work_struct hotplug_work;
struct work_struct audio_work;
--
1.7.7.5
_______________________________________________
dri-devel mailing list
dri-devel@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/dri-devel
