On Thu, May 4, 2023 at 6:12 AM Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> wrote: > > Am Mittwoch, 3. Mai 2023, 18:33:07 CEST schrieb Frieder Schrempf: > > From: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx> > > > > The datasheet describes the following initialization flow including > > minimum delay times between each step: > > > > 1. DSI data lanes need to be in LP-11 and the clock lane in HS mode > > 2. toggle EN signal > > 3. initialize registers > > 4. enable PLL > > 5. soft reset > > 6. enable DSI stream > > 7. check error status register > > > > To meet this requirement we need to make sure the host bridge's > > pre_enable() is called first by using the pre_enable_prev_first > > flag. > > > > Furthermore we need to split enable() into pre_enable() which covers > > steps 2-5 from above and enable() which covers step 7 and is called > > after the host bridge's enable(). > > > > Signed-off-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx> > > Tested-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> #TQMa8MxML/MBa8Mx Should this have a Fixes tag so that it could be backported to stable kernels?
