On 06/09/2013 09:32 PM, Russell King wrote:
The npix/nline registers are supposed to be programmed with the total number of pixels/lines, not the displayed pixels/lines, and not minus one either. Signed-off-by: Russell King<rmk+kernel@xxxxxxxxxxxxxxxx> ---
Russell, Rob, I have patches fixing TDA998x sync generation for progressive video. They are based on TDA9983b datasheet [1]. TDA998x expects ITU-style sync with positive hblank/vblank (or VESA-style hsync/vsync plus refpix/refline). The patches make TDA998x behave as transparent as possible, i.e. invert input sync signals as required and revert for output sync as requested by EDID. I have measured a bunch of modes with an oszilloscope near-end (TDA998x input) and far-end (DVI receiver output) and they are pixel- and line-true. Unfortunately, I have no receiver allowing me to also fix interlaced sync generation but with progressive working, that shouldn't be that hard to implement. Will clean-up patches next week and rebase on Russell's RFC. Sebastian [1] http://pdf1.alldatasheet.com/datasheet-pdf/view/347888/NXP/TDA9983B.html _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
