On Wed, Dec 07, 2022 at 02:00:10PM -0800, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> > > Define the display clock controllers, the MDSS instances, the DP phys > and connect these together. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> > Signed-off-by: Bjorn Andersson <quic_bjorande@xxxxxxxxxxx> > --- > > Changes since v4: > - None > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +++++++++++++++++++++++++ > 1 file changed, 838 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 9f3132ac2857..c2f186495506 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > + mdss0: display-subsystem@ae00000 { > + compatible = "qcom,sc8280xp-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + power-domains = <&dispcc0 MDSS_GDSC>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", > + "ahb", > + "core"; > + > + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + iommus = <&apps_smmu 0x1000 0x402>; > + > + status = "disabled"; Please move status last. > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss0_mdp: display-controller@ae01000 { [...] > + mdss1: display-subsystem@22000000 { > + compatible = "qcom,sc8280xp-mdss"; > + reg = <0 0x22000000 0 0x1000>; > + reg-names = "mdss"; > + > + power-domains = <&dispcc1 MDSS_GDSC>; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, > + <&dispcc1 DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", > + "ahb", > + "core"; > + > + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; > + > + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + iommus = <&apps_smmu 0x1800 0x402>; > + > + status = "disabled"; Same here. > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss1_mdp: display-controller@22001000 { Johan