The rockchip phy can be convigured in ttl mode. The phy is shared between lvds, dsi, ttl. The configuration that now I'm able to support has the display output on some set of pins on standard vop output and a set of pins using the ttl phy. The solution is not clean as I would like to have because some register that are used to enable the TTL, are in the same register area of the dsi controller. In order to test I must add the following dsi_dphy: phy@ff2e0000 { reg = <0x0 0xff2e0000 0x0 0x10000>, <0x0 0xff450000 0x0 0x10000>; ... } The problem here is the second region I have added is the same of dsi logic. Only one register is needed by the the phy driver Michael Trimarchi (4): phy: add PHY_MODE_TTL phy: rockchip: Add inno_is_valid_phy_mode phy: rockchip: Implement TTY phy mode drm/rockchip: rgb: Add dphy connection to rgb output drivers/gpu/drm/rockchip/rockchip_rgb.c | 18 +++++ .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 72 +++++++++++++++++++ include/linux/phy/phy.h | 3 +- 3 files changed, 92 insertions(+), 1 deletion(-) -- 2.34.1