Hi Sascha,
On 8/15/22 15:39, Sascha Hauer wrote:
> The hsync/vsync polarities were not honoured for the eDP and HDMI ports.
> Add the register settings to configure the polarities as requested by the
> DRM_MODE_FLAG_PHSYNC/DRM_MODE_FLAG_PVSYNC flags.
Amazingly enough it worked even without this fix in my setup (Radxa
ROCK3 Model A + HP 27f 4k monitor). Hence I can only say that this patch
does not break anything in my setup :-)
Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") ?
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Tested-by: Michael Riesch <michael.riesch@xxxxxxxxxxxxxx>
Thanks and best regards,
Michael
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> index e4631f515ba42..f9aa8b96c6952 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> @@ -1439,11 +1439,15 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id,
> die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
> die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
> FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
> + dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
> + dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
> break;
> case ROCKCHIP_VOP2_EP_EDP0:
> die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
> die |= RK3568_SYS_DSP_INFACE_EN_EDP |
> FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
> + dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
> + dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
> break;
> case ROCKCHIP_VOP2_EP_MIPI0:
> die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;
