Hi,
Tested it on gru-kevin with mainline kernel 5.19 and it works
On Tue, 2021-10-19 at 22:58, Hugh Cole-Baker wrote:
> The VOP on RK3399 has a different approach from previous versions for
> setting a gamma lookup table, using an update_gamma_lut register. As
> this differs from RK3288, give RK3399 its own set of "common" register
> definitions.
>
> Signed-off-by: Hugh Cole-Baker <sigmaris@xxxxxxxxx>
Tested-by: "Milan P. Stanić" <mps@xxxxxxxxxxx>
> ---
>
> Changes from v1: no changes in this patch
>
> drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++
> drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++--
> drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 +
> 3 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> index 857d97cdc67c..14179e89bd21 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> @@ -99,6 +99,8 @@ struct vop_common {
> struct vop_reg dither_down_en;
> struct vop_reg dither_up;
> struct vop_reg dsp_lut_en;
> + struct vop_reg update_gamma_lut;
> + struct vop_reg lut_buffer_index;
> struct vop_reg gate_en;
> struct vop_reg mmu_en;
> struct vop_reg out_mode;
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> index ca7cc82125cb..bfb7e130f09b 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> @@ -865,6 +865,24 @@ static const struct vop_output rk3399_output = {
> .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
> };
>
> +static const struct vop_common rk3399_common = {
> + .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22),
> + .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
> + .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20),
> + .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4),
> + .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3),
> + .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2),
> + .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1),
> + .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
> + .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0),
> + .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7),
> + .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1),
> + .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
> + .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
> + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
> + .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
> +};
> +
> static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = {
> .y2r_coefficients = {
> VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0),
> @@ -944,7 +962,7 @@ static const struct vop_data rk3399_vop_big = {
> .version = VOP_VERSION(3, 5),
> .feature = VOP_FEATURE_OUTPUT_RGB10,
> .intr = &rk3366_vop_intr,
> - .common = &rk3288_common,
> + .common = &rk3399_common,
> .modeset = &rk3288_modeset,
> .output = &rk3399_output,
> .afbc = &rk3399_vop_afbc,
> @@ -952,6 +970,7 @@ static const struct vop_data rk3399_vop_big = {
> .win = rk3399_vop_win_data,
> .win_size = ARRAY_SIZE(rk3399_vop_win_data),
> .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data,
> + .lut_size = 1024,
> };
>
> static const struct vop_win_data rk3399_vop_lit_win_data[] = {
> @@ -970,13 +989,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = {
> static const struct vop_data rk3399_vop_lit = {
> .version = VOP_VERSION(3, 6),
> .intr = &rk3366_vop_intr,
> - .common = &rk3288_common,
> + .common = &rk3399_common,
> .modeset = &rk3288_modeset,
> .output = &rk3399_output,
> .misc = &rk3368_misc,
> .win = rk3399_vop_lit_win_data,
> .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
> .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data,
> + .lut_size = 256,
> };
>
> static const struct vop_win_data rk3228_vop_win_data[] = {
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
> index 0b3cd65ba5c1..406e981c75bd 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
> @@ -628,6 +628,7 @@
> #define RK3399_YUV2YUV_WIN 0x02c0
> #define RK3399_YUV2YUV_POST 0x02c4
> #define RK3399_AUTO_GATING_EN 0x02cc
> +#define RK3399_DBG_POST_REG1 0x036c
> #define RK3399_WIN0_CSC_COE 0x03a0
> #define RK3399_WIN1_CSC_COE 0x03c0
> #define RK3399_WIN2_CSC_COE 0x03e0
