Hi, Rob: You have ask Nancy question in old version and Nancy has reply in [1], how do you think about Nancy's reply? [1] http://lists.infradead.org/pipermail/linux-mediatek/2022-April/039890.html Regards, CK On Mon, 2022-06-20 at 17:19 +0800, Nancy.Lin wrote: > Add vdosys1 RDMA definition. > > Signed-off-by: Nancy.Lin <nancy.lin@xxxxxxxxxxxx> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@xxxxxxxxxxxxx> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > Tested-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@xxxxxxxxxxxxx> > --- > .../display/mediatek/mediatek,mdp-rdma.yaml | 88 > +++++++++++++++++++ > 1 file changed, 88 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > rdma.yaml > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > rdma.yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > rdma.yaml > new file mode 100644 > index 000000000000..dd12e2ff685c > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > rdma.yaml > @@ -0,0 +1,88 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2V-LPisZwDTVUkpQ5cJnZhaUV4iBSohT_B1_8bY3yar4Iuacq_NaTManclYLSA$ > > +$schema: > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2V-LPisZwDTVUkpQ5cJnZhaUV4iBSohT_B1_8bY3yar4Iuacq_NaTMZYdJgbgQ$ > > + > +title: MediaTek MDP RDMA > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@xxxxxxxxxx> > + - Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> > + > +description: > + The MediaTek MDP RDMA stands for Read Direct Memory Access. > + It provides real time data to the back-end panel driver, such as > DSI, > + DPI and DP_INTF. > + It contains one line buffer to store the sufficient pixel data. > + RDMA device node must be siblings to the central MMSYS_CONFIG > node. > + For a description of the MMSYS_CONFIG binding, see > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > for details. > + > +properties: > + compatible: > + const: mediatek,mt8195-vdo1-rdma > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: RDMA Clock > + > + iommus: > + maxItems: 1 > + > + mediatek,gce-client-reg: > + description: > + The register of display function block to be set by gce. There > are 4 arguments, > + such as gce node, subsys id, offset and register size. The > subsys id that is > + mapping to the register of display function blocks is defined > in the gce header > + include/dt-bindings/gce/<chip>-gce.h of each chips. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle of GCE > + - description: GCE subsys id > + - description: register offset > + - description: register size > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - power-domains > + - clocks > + - iommus > + - mediatek,gce-client-reg > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/power/mt8195-power.h> > + #include <dt-bindings/gce/mt8195-gce.h> > + #include <dt-bindings/memory/mt8195-memory-port.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + rdma@1c104000 { > + compatible = "mediatek,mt8195-vdo1-rdma"; > + reg = <0 0x1c104000 0 0x1000>; > + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; > + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 > 0x1000>; > + }; > + };