Subject prefix should be drm/edid.
On Sun, 13 Feb 2022, Yaroslav Bolyukin <iam@xxxxxxx> wrote:
> As per DisplayID v2.0 Errata E9 spec
Please be more elaborate about the changes.
You also need to update drm_reset_display_info().
BR,
Jani.
> Signed-off-by: Yaroslav Bolyukin <iam@xxxxxxx>
> ---
> drivers/gpu/drm/drm_edid.c | 31 ++++++++++++++++++++-----------
> include/drm/drm_connector.h | 6 ++++++
> include/drm/drm_displayid.h | 4 ++++
> 3 files changed, 30 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index a7663f9a1..83ee685c8 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5270,7 +5270,7 @@ static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
> return;
>
> - if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
> + if (block->num_bytes < 5) {
> drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
> return;
> }
> @@ -5290,20 +5290,29 @@ static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> break;
> }
>
> - if (!info->mso_stream_count) {
> - info->mso_pixel_overlap = 0;
> - return;
> + info->mso_pixel_overlap = 0;
> +
> + if (info->mso_stream_count) {
> + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
> + if (info->mso_pixel_overlap > 8) {
> + drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
> + info->mso_pixel_overlap);
> + info->mso_pixel_overlap = 8;
> + }
> +
> + drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
> + info->mso_stream_count, info->mso_pixel_overlap);
> }
>
> - info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
> - if (info->mso_pixel_overlap > 8) {
> - drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
> - info->mso_pixel_overlap);
> - info->mso_pixel_overlap = 8;
> + if (block->num_bytes < 7) {
> + /* DSC bpp is optional */
> + return;
> }
>
> - drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
> - info->mso_stream_count, info->mso_pixel_overlap);
> + info->dp_dsc_bpp = FIELD_GET(DISPLAYID_VESA_DSC_BPP_INT, vesa->dsc_bpp_int) * 16 +
> + FIELD_GET(DISPLAYID_VESA_DSC_BPP_FRACT, vesa->dsc_bpp_fract);
> +
> + drm_dbg_kms(connector->dev, "DSC bits per pixel %u\n", info->dp_dsc_bpp);
> }
>
> static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 5e36eb3df..04ef0e995 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -634,6 +634,12 @@ struct drm_display_info {
> * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
> */
> u8 mso_pixel_overlap;
> +
> + /**
> + * @dp_dsc_bpp: DP Display-Stream-Compression (DSC) timing's target
> + * DST bits per pixel in 6.4 fixed point format. 0 means undefined
> + */
> + u16 dp_dsc_bpp;
> };
>
> int drm_display_info_set_bus_formats(struct drm_display_info *info,
> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
> index 7ffbd9f7b..1be6deddc 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -131,12 +131,16 @@ struct displayid_detailed_timing_block {
>
> #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
> #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
> +#define DISPLAYID_VESA_DSC_BPP_INT GENMASK(5, 0)
> +#define DISPLAYID_VESA_DSC_BPP_FRACT GENMASK(3, 0)
>
> struct displayid_vesa_vendor_specific_block {
> struct displayid_block base;
> u8 oui[3];
> u8 data_structure_type;
> u8 mso;
> + u8 dsc_bpp_int;
> + u8 dsc_bpp_fract;
> } __packed;
>
> /* DisplayID iteration */
>
> base-commit: 1528038385c0a706aac9ac165eeb24044fef6825
--
Jani Nikula, Intel Open Source Graphics Center
