These are minor cleanups for drm_pcie_get_speed_cap_mask() to use
standard #defines and PCIe capability accessors. They depend on
a pci_regs.h change (130f1b8f35) that appeared in v3.8-rc2.
They don't address the issue of DRM devices directly below a host
bridge that doesn't appear as a PCI device (the issue Lucas has
been working on).
I'm a little skeptical about the premise of drm_pcie_get_speed_cap_mask()
to begin with. Link speed seems like something fairly generic that should
be handled in the core, not in individual drivers. Sec 6.11, "Link Speed
Management", in the PCIe 3.0 spec seems relevant and suggests that the
hardware should automatically use the highest speed supported by both ends
of the link unless software sets a lower maximum via Target Link Speed.
But I can't match up the code, e.g., evergreen_pcie_gen2_enable(), to
anything in the generic PCIe specs, so maybe this driver code is
essentially quirks for misbehaving hardware?
---
Bjorn Helgaas (3):
drm/pci: Use the standard #defines for PCIe Link Capability bits
drm/pci: Set all supported speeds in speed cap mask for pre-3.0 devices
drm/pci: Use PCI Express Capability accessors
drivers/gpu/drm/drm_pci.c | 27 ++++++++-------------------
1 files changed, 8 insertions(+), 19 deletions(-)
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