On Tue, Dec 11, 2012 at 11:56 AM, <j.glisse@xxxxxxxxx> wrote: > From: Jerome Glisse <jglisse@xxxxxxxxxx> > > Set the proper number of tile pipe that should be a multiple of > pipe depending on the number of se engine. > > Fix: > https://bugs.freedesktop.org/show_bug.cgi?id=56405 > https://bugs.freedesktop.org/show_bug.cgi?id=56720 > > v2: Don't change sumo2 > > Signed-off-by: Jerome Glisse <jglisse@xxxxxxxxxx> > Cc: stable@xxxxxxxxxxxxxxx Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/radeon/evergreen.c | 8 ++++---- > drivers/gpu/drm/radeon/evergreend.h | 2 ++ > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c > index 14313ad..b957de1 100644 > --- a/drivers/gpu/drm/radeon/evergreen.c > +++ b/drivers/gpu/drm/radeon/evergreen.c > @@ -1819,7 +1819,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) > case CHIP_SUMO: > rdev->config.evergreen.num_ses = 1; > rdev->config.evergreen.max_pipes = 4; > - rdev->config.evergreen.max_tile_pipes = 2; > + rdev->config.evergreen.max_tile_pipes = 4; > if (rdev->pdev->device == 0x9648) > rdev->config.evergreen.max_simds = 3; > else if ((rdev->pdev->device == 0x9647) || > @@ -1842,7 +1842,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) > rdev->config.evergreen.sc_prim_fifo_size = 0x40; > rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; > rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; > - gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; > + gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN; > break; > case CHIP_SUMO2: > rdev->config.evergreen.num_ses = 1; > @@ -1864,7 +1864,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) > rdev->config.evergreen.sc_prim_fifo_size = 0x40; > rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; > rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; > - gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; > + gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN; > break; > case CHIP_BARTS: > rdev->config.evergreen.num_ses = 2; > @@ -1912,7 +1912,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) > break; > case CHIP_CAICOS: > rdev->config.evergreen.num_ses = 1; > - rdev->config.evergreen.max_pipes = 4; > + rdev->config.evergreen.max_pipes = 2; > rdev->config.evergreen.max_tile_pipes = 2; > rdev->config.evergreen.max_simds = 2; > rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; > diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h > index df542f1..52c89c9 100644 > --- a/drivers/gpu/drm/radeon/evergreend.h > +++ b/drivers/gpu/drm/radeon/evergreend.h > @@ -45,6 +45,8 @@ > #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 > #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 > #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 > +#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 > +#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 > > /* Registers */ > > -- > 1.7.11.7 > > _______________________________________________ > dri-devel mailing list > dri-devel@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
