[drm:i915-display-struct-refactor 22/25] drivers/gpu/drm/i915/gvt/handlers.c:510:34: error: no member named 'dpll' in 'struct drm_i915_private'

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tree:   git://people.freedesktop.org/~airlied/linux.git i915-display-struct-refactor
head:   e183b125871ffdd77b6de15a963e6fc8a47173c9
commit: 5b99cab055595d1b12d7425e560b5a9fcd15c9a3 [22/25] drm/i915/display: move dpll struct into display
config: x86_64-randconfig-a016-20210906 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 6fe2beba7d2a41964af658c8c59dd172683ef739)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git remote add drm git://people.freedesktop.org/~airlied/linux.git
        git fetch --no-tags drm i915-display-struct-refactor
        git checkout 5b99cab055595d1b12d7425e560b5a9fcd15c9a3
        # save the attached .config to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gvt/handlers.c:510:34: error: no member named 'dpll' in 'struct drm_i915_private'
                           refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc;
                                    ~~~~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/i915/gvt/handlers.c:541:36: error: no member named 'dpll' in 'struct drm_i915_private'
           int refclk = vgpu->gvt->gt->i915->dpll.ref_clks.nssc;
                        ~~~~~~~~~~~~~~~~~~~  ^
   2 errors generated.


vim +510 drivers/gpu/drm/i915/gvt/handlers.c

04d348ae3f0aea Zhi Wang 2016-04-25  446  
6a4500c7b83f9e Colin Xu 2021-02-26  447  /*
6a4500c7b83f9e Colin Xu 2021-02-26  448   * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to
6a4500c7b83f9e Colin Xu 2021-02-26  449   *   TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on
6a4500c7b83f9e Colin Xu 2021-02-26  450   *   setup_virtual_dp_monitor().
6a4500c7b83f9e Colin Xu 2021-02-26  451   * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled
6a4500c7b83f9e Colin Xu 2021-02-26  452   *   DPLL. Later guest driver may setup a different DPLLx when setting mode.
6a4500c7b83f9e Colin Xu 2021-02-26  453   * So the correct sequence to find DP stream clock is:
6a4500c7b83f9e Colin Xu 2021-02-26  454   *   Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x.
6a4500c7b83f9e Colin Xu 2021-02-26  455   *   Check correct PLLx for PORT_x to get PLL frequency and DP bitrate.
6a4500c7b83f9e Colin Xu 2021-02-26  456   * Then Refresh rate then can be calculated based on follow equations:
6a4500c7b83f9e Colin Xu 2021-02-26  457   *   Pixel clock = h_total * v_total * refresh_rate
6a4500c7b83f9e Colin Xu 2021-02-26  458   *   stream clock = Pixel clock
6a4500c7b83f9e Colin Xu 2021-02-26  459   *   ls_clk = DP bitrate
6a4500c7b83f9e Colin Xu 2021-02-26  460   *   Link M/N = strm_clk / ls_clk
6a4500c7b83f9e Colin Xu 2021-02-26  461   */
6a4500c7b83f9e Colin Xu 2021-02-26  462  
6a4500c7b83f9e Colin Xu 2021-02-26  463  static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
6a4500c7b83f9e Colin Xu 2021-02-26  464  {
6a4500c7b83f9e Colin Xu 2021-02-26  465  	u32 dp_br = 0;
6a4500c7b83f9e Colin Xu 2021-02-26  466  	u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));
6a4500c7b83f9e Colin Xu 2021-02-26  467  
6a4500c7b83f9e Colin Xu 2021-02-26  468  	switch (ddi_pll_sel) {
6a4500c7b83f9e Colin Xu 2021-02-26  469  	case PORT_CLK_SEL_LCPLL_2700:
6a4500c7b83f9e Colin Xu 2021-02-26  470  		dp_br = 270000 * 2;
6a4500c7b83f9e Colin Xu 2021-02-26  471  		break;
6a4500c7b83f9e Colin Xu 2021-02-26  472  	case PORT_CLK_SEL_LCPLL_1350:
6a4500c7b83f9e Colin Xu 2021-02-26  473  		dp_br = 135000 * 2;
6a4500c7b83f9e Colin Xu 2021-02-26  474  		break;
6a4500c7b83f9e Colin Xu 2021-02-26  475  	case PORT_CLK_SEL_LCPLL_810:
6a4500c7b83f9e Colin Xu 2021-02-26  476  		dp_br = 81000 * 2;
6a4500c7b83f9e Colin Xu 2021-02-26  477  		break;
6a4500c7b83f9e Colin Xu 2021-02-26  478  	case PORT_CLK_SEL_SPLL:
6a4500c7b83f9e Colin Xu 2021-02-26  479  	{
6a4500c7b83f9e Colin Xu 2021-02-26  480  		switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {
6a4500c7b83f9e Colin Xu 2021-02-26  481  		case SPLL_FREQ_810MHz:
6a4500c7b83f9e Colin Xu 2021-02-26  482  			dp_br = 81000 * 2;
6a4500c7b83f9e Colin Xu 2021-02-26  483  			break;
6a4500c7b83f9e Colin Xu 2021-02-26  484  		case SPLL_FREQ_1350MHz:
6a4500c7b83f9e Colin Xu 2021-02-26  485  			dp_br = 135000 * 2;
6a4500c7b83f9e Colin Xu 2021-02-26  486  			break;
6a4500c7b83f9e Colin Xu 2021-02-26  487  		case SPLL_FREQ_2700MHz:
6a4500c7b83f9e Colin Xu 2021-02-26  488  			dp_br = 270000 * 2;
6a4500c7b83f9e Colin Xu 2021-02-26  489  			break;
6a4500c7b83f9e Colin Xu 2021-02-26  490  		default:
6a4500c7b83f9e Colin Xu 2021-02-26  491  			gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n",
6a4500c7b83f9e Colin Xu 2021-02-26  492  				    vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));
6a4500c7b83f9e Colin Xu 2021-02-26  493  			break;
6a4500c7b83f9e Colin Xu 2021-02-26  494  		}
6a4500c7b83f9e Colin Xu 2021-02-26  495  		break;
6a4500c7b83f9e Colin Xu 2021-02-26  496  	}
6a4500c7b83f9e Colin Xu 2021-02-26  497  	case PORT_CLK_SEL_WRPLL1:
6a4500c7b83f9e Colin Xu 2021-02-26  498  	case PORT_CLK_SEL_WRPLL2:
6a4500c7b83f9e Colin Xu 2021-02-26  499  	{
6a4500c7b83f9e Colin Xu 2021-02-26  500  		u32 wrpll_ctl;
6a4500c7b83f9e Colin Xu 2021-02-26  501  		int refclk, n, p, r;
6a4500c7b83f9e Colin Xu 2021-02-26  502  
6a4500c7b83f9e Colin Xu 2021-02-26  503  		if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1)
6a4500c7b83f9e Colin Xu 2021-02-26  504  			wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));
6a4500c7b83f9e Colin Xu 2021-02-26  505  		else
6a4500c7b83f9e Colin Xu 2021-02-26  506  			wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));
6a4500c7b83f9e Colin Xu 2021-02-26  507  
6a4500c7b83f9e Colin Xu 2021-02-26  508  		switch (wrpll_ctl & WRPLL_REF_MASK) {
6a4500c7b83f9e Colin Xu 2021-02-26  509  		case WRPLL_REF_PCH_SSC:
6a4500c7b83f9e Colin Xu 2021-02-26 @510  			refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc;
6a4500c7b83f9e Colin Xu 2021-02-26  511  			break;
6a4500c7b83f9e Colin Xu 2021-02-26  512  		case WRPLL_REF_LCPLL:
6a4500c7b83f9e Colin Xu 2021-02-26  513  			refclk = 2700000;
6a4500c7b83f9e Colin Xu 2021-02-26  514  			break;
6a4500c7b83f9e Colin Xu 2021-02-26  515  		default:
6a4500c7b83f9e Colin Xu 2021-02-26  516  			gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n",
6a4500c7b83f9e Colin Xu 2021-02-26  517  				    vgpu->id, port_name(port), wrpll_ctl);
6a4500c7b83f9e Colin Xu 2021-02-26  518  			goto out;
6a4500c7b83f9e Colin Xu 2021-02-26  519  		}
6a4500c7b83f9e Colin Xu 2021-02-26  520  
6a4500c7b83f9e Colin Xu 2021-02-26  521  		r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK;
6a4500c7b83f9e Colin Xu 2021-02-26  522  		p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
6a4500c7b83f9e Colin Xu 2021-02-26  523  		n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
6a4500c7b83f9e Colin Xu 2021-02-26  524  
6a4500c7b83f9e Colin Xu 2021-02-26  525  		dp_br = (refclk * n / 10) / (p * r) * 2;
6a4500c7b83f9e Colin Xu 2021-02-26  526  		break;
6a4500c7b83f9e Colin Xu 2021-02-26  527  	}
6a4500c7b83f9e Colin Xu 2021-02-26  528  	default:
6a4500c7b83f9e Colin Xu 2021-02-26  529  		gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n",
6a4500c7b83f9e Colin Xu 2021-02-26  530  			    vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));
6a4500c7b83f9e Colin Xu 2021-02-26  531  		break;
6a4500c7b83f9e Colin Xu 2021-02-26  532  	}
6a4500c7b83f9e Colin Xu 2021-02-26  533  
6a4500c7b83f9e Colin Xu 2021-02-26  534  out:
6a4500c7b83f9e Colin Xu 2021-02-26  535  	return dp_br;
6a4500c7b83f9e Colin Xu 2021-02-26  536  }
6a4500c7b83f9e Colin Xu 2021-02-26  537  

:::::: The code at line 510 was first introduced by commit
:::::: 6a4500c7b83f9e4470dd20cf89f691abd132d090 drm/i915/gvt: Get accurate vGPU virtual display refresh rate from vreg

:::::: TO: Colin Xu <colin.xu@xxxxxxxxx>
:::::: CC: Zhenyu Wang <zhenyuw@xxxxxxxxxxxxxxx>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip


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