On 2021-07-05 at 14:53:08 +0100, Matthew Auld wrote: > It's a noop on DG1, and in the future when need to support other devices > which let us control the coherency, then it should be an immutable > creation time property for the BO. This will likely be controlled > through a new gem_create_ext extension. > > v2: add some kernel doc for the discrete changes, and document the > implicit rules LGTM Reviewed-by: Ramalingam C <ramalingam.c@xxxxxxxxx> > > Suggested-by: Daniel Vetter <daniel@xxxxxxxx> > Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx> > Cc: Thomas Hellström <thomas.hellstrom@xxxxxxxxxxxxxxx> > Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx> > Cc: Jordan Justen <jordan.l.justen@xxxxxxxxx> > Cc: Kenneth Graunke <kenneth@xxxxxxxxxxxxx> > Cc: Jason Ekstrand <jason@xxxxxxxxxxxxxx> > Cc: Daniel Vetter <daniel.vetter@xxxxxxxx> > Cc: Ramalingam C <ramalingam.c@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 +++++ > include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++- > 2 files changed, 34 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > index 7d1400b13429..43004bef55cb 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > @@ -268,6 +268,9 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, > struct drm_i915_gem_object *obj; > int err = 0; > > + if (IS_DGFX(to_i915(dev))) > + return -ENODEV; > + > rcu_read_lock(); > obj = i915_gem_object_lookup_rcu(file, args->handle); > if (!obj) { > @@ -303,6 +306,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, > enum i915_cache_level level; > int ret = 0; > > + if (IS_DGFX(i915)) > + return -ENODEV; > + > switch (args->caching) { > case I915_CACHING_NONE: > level = I915_CACHE_NONE; > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index d13c6c5fad04..a4faceeb8c32 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -1372,7 +1372,34 @@ struct drm_i915_gem_busy { > * require unbinding the object from the GTT first, if its current caching value > * doesn't match. > * > - * > + * Note that this all changes on discrete platforms, starting from DG1, the > + * set/get caching is no longer supported, and is now rejected. Instead the CPU > + * caching attributes(WB vs WC) will become an immutable creation time property > + * for the object, along with the GTT caching level. For now we don't expose any > + * new uAPI for this, instead on DG1 this is all implicit, although this largely > + * shouldn't matter since DG1 is coherent by default(without any way of > + * controlling it). > + * > + * Implicit caching rules, starting from DG1: > + * > + * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) > + * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and > + * mapped as write-combined only. > + * > + * - Everything else is always allocated and mapped as write-back, with the > + * guarantee that everything is also coherent with the GPU. > + * > + * Note that this is likely to change in the future again, where we might need > + * more flexibility on future devices, so making this all explicit as part of a > + * new &drm_i915_gem_create_ext extension is probable. > + * > + * Side note: Part of the reason for this is that changing the at-allocation-time CPU > + * caching attributes for the pages might be required(and is expensive) if we > + * need to then CPU map the pages later with different caching attributes. This > + * inconsistent caching behaviour, while supported on x86, is not universally > + * supported on other architectures. So for simplicity we opt for setting > + * everything at creation time, whilst also making it immutable, on discrete > + * platforms. > */ > struct drm_i915_gem_caching { > /** > -- > 2.26.3 >