On Thu, Nov 01, 2012 at 11:39:58PM +0100, Daniel Vetter wrote: > On Thu, Nov 01, 2012 at 10:12:21AM -0700, Jesse Barnes wrote: > > On Thu, 1 Nov 2012 19:07:02 +0200 > > Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > > > > > On Thu, Nov 01, 2012 at 07:39:12AM -0700, Jesse Barnes wrote: > > > > On Thu, 1 Nov 2012 12:12:35 +0100 > > > > Daniel Vetter <daniel@xxxxxxxx> wrote: > > > > > > > > > On Thu, Oct 25, 2012 at 8:05 PM, <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > > > > > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > > > > > > > > > Send completion events when the atomic modesetting operations has > > > > > > finished succesfully. > > > > > > > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > > > > > > > I have to admit I'm not on top of the latest ioctl/interface > > > > > discussion, but one new requirement for the modeset (not the pageflip > > > > > part) of the all this atomic stuff I've discovered is that the kernel > > > > > needs to be able to select the crtcs for each output completely > > > > > unrestricted. I think userspace should simply pass in abstract crtc > > > > > ids (e.g. 0, 1, 2, ...) and the kernel then passes back the actual > > > > > crtcs it has selected. > > > > > > > > > > We can't do that remapping internally because the crtc abstraction is leaky: > > > > > - wait_for_vblank requires the pipe id, which could then change on every modeset > > > > > - similarly userspace doing MI_WAIT for scanlines needs to know the > > > > > actual hw pipe in use by a crtc. > > > > > And current userspace presumes that the mapping between crtc->pipe > > > > > doesn't change. > > > > > > > > > > An example why the kernel needs to pick the crtc for userspace: > > > > > - on ivb only pipe A has a 7x5 panel fitter, so usually you want to > > > > > put the panel on the first crtc > > > > > - but if you run in a 3 pipe configuration and have an eDP panel, it's > > > > > better to put the eDP output on pipe C, since then pipes A&B will have > > > > > full 4-lane fdi links to the pch ports (instead of otherwise only 2 > > > > > lanes each on links B&C) > > > > > - similarly when we have a 3 pipe configuration with all encoders on > > > > > the pch, we need to move the mode with the highest dotclock to pipe A > > > > > (since that's the only one which will have 4 lanes, pipe B&C will only > > > > > have 2 each). > > > > > - afaik these kind of asymmetric constraints won't disappear anytime > > > > > soon, haswell definitely still has some. > > > > > > > > Yeah that's a good point... adding a virtual crtc layer would solve > > > > this and let us preserve the existing ABI. > > > > > > How would the state handling work? I mean if drm_crtc X currently has > > > some state, drm_crtc Y has some other state, and then we do a modeset > > > which would require swapping the roles of the crtcs, what would happen > > > to the bits of state that we didn't specify? > > > > > > If we'd do the remapping below the drm crtc layer, the state would > > > always be tied to the drm crtc. But that would definitely require > > > mostly uniform hardware "crtcs" so that the capabilities of the > > > drm_crtcs wouldn't keep changing whenever the remap happens. > > > > > > Well, I suppose we could tie the state to the virtual crtc instead, > > > and doing an operation on a real drm_crtc would also change the > > > state of the currently bound virtual crtc. And then changing the > > > virtual<->real mapping would just copy the state over from the virtual > > > crtc to the real drm_crtc. > > > > > > And if we do it for crtcs, then we'd need to do it for planes as well, > > > because the plane<->crtc mapping can be fixed or otherwise limited > > > in some fashion. > > > > > > Either way it sounds rather messy to me. > > > > > > Another option would be just leave it up to userspace to make the > > > correct choice between crtcs and planes. But then user space needs > > > to be equipped with more hardware specific knowledge, so it's not > > > a very appealing idea either. > > > > Yeah it gets ugly one way or another. From a userspace perspective, > > keeping the ugliness in the kernel is nice, and if we have to do it > > somewhere I guess I'd prefer that. > > My tentative Grand Plan (tm) for the atomic modeset implementation of such > things is to pimp the new struct intel_crtc_config to contain all the > configuration state (so with Rob's atomic modeset proposal that would also > embed the drm_crtc_state struct). It would also contain all the derived > state like pll settings, fdi lanes, ... > > Now the improve >mode_adjust stage, now called ->compute_config allocates > such a struct for each crtc, does some prep, calls down into > encoder->compute_config callbacks, then applies any fixups and screaming > required to come up with a working global config. All rather hazy, I know > ;-) > > But e.g. for the above case of trying to squeeze the fdi links into the > available sets of fdi lanes I guess we could first compute the upper bound > for the fdi link requirements (the current wip stuff already pre-computes > the pipe_bpp from the fb->depth). Then check whether that fits, do any > readjustments (I already have a has_pch_encoder attribute, maybe at the > wrong spot still, but we should be able to know which outputs need fdi > links). If there's no way to fit it, reassign pipes a bit or try > dithering. Once that works, call into encoders ... > > Or maybe we could do a loop, since the encoders also limit the pipe_bpp. > So first pipe_bpp from the fb->depth, then check for output properties > (6bpc dithering on lvds, or a puny dp link), then check whether it fits > into fdi. If not, dither more or reassign, then re-run the encoder config > computations. If it still has too high bw requirementsmuch, give up. > > In any case, and disregarding the above ramblings, I plan to make the > intel_crtc_config thing free-standing for the ->compute_config stage, so > we could easily add a preferred_crtc pointer to it since it's not tied to > a specific crtc at that point. The problem now is that the > connector->encoder->crtc links are embedded into the connectors and > encoders, so they are not free-standing. But if we want to support atomic > modeset on all properties (which I think we should), we need to fix that > anyway ... I'm not sure what the placement of the encoder and crtc pointers has to do with atomic modeset. Now, all of what you describe above is about the internals, and seems perfectly reasonable. It sounds like the same idea had when I started plaing around with atomic modeset. That is pulling the state out of the various structures into some kind of state object that can be manipulated w/o disturbing the rest of the system. But I gave up on the idea due to the sheer scope of the work, and I wanted to make something that works sooner rather than later. My current code just goes around and shovels the new state into the object structs themselves, relying mostly on the save/restore code to reset the various bits of state to the original values when things fail. But anyway, the user visible state handling is still going to be a problem with them virtual crtcs. We need to come up with a plan for that if that's really the route we want to take. -- Ville Syrjälä Intel OTC _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
