On Fri, Oct 5, 2012 at 10:15 AM, Markus Trippelsdorf
<markus@xxxxxxxxxxxxxxx> wrote:
> On 2012.10.05 at 10:02 -0400, Alex Deucher wrote:
>> On Fri, Oct 5, 2012 at 9:38 AM, Markus Trippelsdorf
>> <markus@xxxxxxxxxxxxxxx> wrote:
>> > On 2012.10.05 at 09:14 -0400, Alex Deucher wrote:
>> >> On Fri, Oct 5, 2012 at 8:37 AM, Markus Trippelsdorf
>> >> <markus@xxxxxxxxxxxxxxx> wrote:
>> >> > When I cold start my machine I see the following error message on my
>> >> > monitor:
>> >> >
>> >> > Out of Range
>> >> > 48.2kHz / 44Hz
>> >> >
>> >> > I have to reboot on older kernel and kexec to the current one to get it
>> >> > working again.
>> >>
>> >> I don't see anything amiss; can you bisect?
>> >
>> > Yes. It's your commit:
>> >
>> > commit 9dbbcfc6894957fdbb311ba92c85c026659878b5
>> > Author: Alex Deucher <alexander.deucher@xxxxxxx>
>> > Date: Wed Sep 12 17:39:57 2012 -0400
>> >
>> > drm/radeon/dce3: use a single PPLL for all DP displays
>>
>> Can you apply the attached patch and send me the output?
>
> [drm] == start crtc 0 driving DVI-D-1 ==
> [drm] crtc 0 is not DP
> [drm] plls in use 0x0
> [drm] crtc 0 using pll 0x1
> [drm] == end crtc 0 ==
Does the attached patch fix the issue?
Alex
From 22044ce8b98127eea9761f3dd86d70abe7dd0a09 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Fri, 5 Oct 2012 10:22:02 -0400
Subject: [PATCH] drm/radeon: allocate PPLLs from low to high
The order shouldn't matter, but there have been problems
reported on certain older asics. This behaves more
like the original code before the PPLL allocation
rework.
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/radeon/atombios_crtc.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 96184d0..2e566e1 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1690,10 +1690,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
}
/* all other cases */
pll_in_use = radeon_get_pll_use_mask(crtc);
- if (!(pll_in_use & (1 << ATOM_PPLL2)))
- return ATOM_PPLL2;
if (!(pll_in_use & (1 << ATOM_PPLL1)))
return ATOM_PPLL1;
+ if (!(pll_in_use & (1 << ATOM_PPLL2)))
+ return ATOM_PPLL2;
DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID;
} else {
@@ -1715,10 +1715,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
}
/* all other cases */
pll_in_use = radeon_get_pll_use_mask(crtc);
- if (!(pll_in_use & (1 << ATOM_PPLL2)))
- return ATOM_PPLL2;
if (!(pll_in_use & (1 << ATOM_PPLL1)))
return ATOM_PPLL1;
+ if (!(pll_in_use & (1 << ATOM_PPLL2)))
+ return ATOM_PPLL2;
DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID;
} else {
--
1.7.7.5
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