Re: [Intel-gfx] [PATCH 2/4] drm/dp: Update DPCD defines

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On 9/20/12 10:10 AM, Paulo Zanoni wrote:
2012/9/18 Adam Jackson <ajax@xxxxxxxxxx>:
Sources: DP, eDP, and DP interop specs, and a VESA slideshow about DP
1.2 for the MST bits.

All I needed to review every bit was DP spec version 1.2.

Lucky you!  I don't have a copy.

+#define DP_SINK_COUNT                      0x200
+# define DP_SINK_COUNT_MASK                (31 << 0)

My DP spec version 1.2 says "bits 7 and 5:0", but the DP 1.1 spec says
it's just 5:0 and "Bits 7 = RESERVED". So should we treat bit 7 as the
most-significant-bit? Notice that this will affect patch 4 of this
series.

Oh, wild. I guess they did that so they could have twice as many downstream devices?

Idea for a follow-up patch: maybe we should try to add some comments
explaining which bits appeared only in some specific DPCD x.y
revision?

That's a good idea.

I'll send follow-ups for that, and to make a DP_GET_SINK_COUNT() that does the right math.

- ajax
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