Hi, Fabien:
Fabien Parent <fparent@xxxxxxxxxxxx> 於 2020年10月23日 週五 下午9:31寫道：
>
> Add DDP support for MT8167 SoC.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@xxxxxxxxxx>
> Signed-off-by: Fabien Parent <fparent@xxxxxxxxxxxx>
> ---
>
> Changelog:
>
> V2: don't set DDP_MUTEX_SOF_DSI{1,2,3} since they are not available on MT8167
>
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 014c1bbe1df2..1f99db6b1a42 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -25,6 +25,19 @@
>
> #define INT_MUTEX BIT(1)
>
> +#define MT8167_MUTEX_MOD_DISP_PWM 1
> +#define MT8167_MUTEX_MOD_DISP_OVL0 6
> +#define MT8167_MUTEX_MOD_DISP_OVL1 7
> +#define MT8167_MUTEX_MOD_DISP_RDMA0 8
> +#define MT8167_MUTEX_MOD_DISP_RDMA1 9
> +#define MT8167_MUTEX_MOD_DISP_WDMA0 10
> +#define MT8167_MUTEX_MOD_DISP_CCORR 11
> +#define MT8167_MUTEX_MOD_DISP_COLOR 12
> +#define MT8167_MUTEX_MOD_DISP_AAL 13
> +#define MT8167_MUTEX_MOD_DISP_GAMMA 14
> +#define MT8167_MUTEX_MOD_DISP_DITHER 15
> +#define MT8167_MUTEX_MOD_DISP_UFOE 16
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -73,6 +86,8 @@
> #define MUTEX_SOF_DPI1 4
> #define MUTEX_SOF_DSI2 5
> #define MUTEX_SOF_DSI3 6
> +#define MT8167_MUTEX_SOF_DPI0 2
> +#define MT8167_MUTEX_SOF_DPI1 3
>
>
> struct mtk_disp_mutex {
> @@ -135,6 +150,21 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
> + [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
> + [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
> + [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
> + [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
> + [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
> + [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
> + [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
> + [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
> [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
> @@ -163,6 +193,13 @@ static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
> [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
> + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> + [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> + [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> +};
> +
> static const struct mtk_ddp_data mt2701_ddp_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -177,6 +214,14 @@ static const struct mtk_ddp_data mt2712_ddp_driver_data = {
> .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> };
>
> +static const struct mtk_ddp_data mt8167_ddp_driver_data = {
> + .mutex_mod = mt8167_mutex_mod,
> + .mutex_sof = mt8167_mutex_sof,
> + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> static const struct mtk_ddp_data mt8173_ddp_driver_data = {
> .mutex_mod = mt8173_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -400,6 +445,8 @@ static const struct of_device_id ddp_driver_dt_match[] = {
> .data = &mt2701_ddp_driver_data},
> { .compatible = "mediatek,mt2712-disp-mutex",
> .data = &mt2712_ddp_driver_data},
> + { .compatible = "mediatek,mt8167-disp-mutex",
> + .data = &mt8167_ddp_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = &mt8173_ddp_driver_data},
> {},
> --
> 2.28.0
>
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