> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@xxxxxxxxx>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx; Shankar, Uma <uma.shankar@xxxxxxxxx>;
> Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx>; ville.syrjala@xxxxxxxxxxxxxxx;
> Sharma, Swati2 <swati2.sharma@xxxxxxxxx>
> Subject: [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block
>
> From: Swati Sharma <swati2.sharma@xxxxxxxxx>
>
> This patch parses MAX_FRL field to get the MAX rate in Gbps that the HDMI 2.1
> panel can support in FRL mode. Source need this field to determine the optimal
> rate between the source and sink during FRL training.
>
> Signed-off-by: Sharma, Swati2 <swati2.sharma@xxxxxxxxx>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
> ---
> drivers/gpu/drm/drm_edid.c | 51 +++++++++++++++++++++++++++++++++++++
> include/drm/drm_connector.h | 6 +++++
> 2 files changed, 57 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 631125b46e04..8afb136e73f5 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4849,6 +4849,52 @@ static void drm_parse_vcdb(struct drm_connector
> *connector, const u8 *db)
> info->rgb_quant_range_selectable = true; }
>
> +static
> +void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8
> +*max_rate_per_lane) {
> + switch(max_frl_rate) {
> + case 1:
> + *max_lanes = 3;
> + *max_rate_per_lane = 3;
> + break;
> + case 2:
> + *max_lanes = 3;
> + *max_rate_per_lane = 6;
> + break;
> + case 3:
> + *max_lanes = 4;
> + *max_rate_per_lane = 6;
> + break;
> + case 4:
> + *max_lanes = 4;
> + *max_rate_per_lane = 8;
> + break;
> + case 5:
> + *max_lanes = 4;
> + *max_rate_per_lane = 10;
> + break;
> + case 6:
> + *max_lanes = 4;
> + *max_rate_per_lane = 12;
> + break;
> + case 0:
> + default:
> + *max_lanes = 0;
> + *max_rate_per_lane = 0;
> + }
> +}
> +
> +static void drm_parse_hdmi_21_additional_fields(struct drm_connector
> *connector,
> + const u8 *db)
> +{
> + struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
> + u8 max_frl_rate;
> +
> + max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
This seems wrong, we need to right shift this by 4 to get the max_frl_rate.
> + drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
> + &hdmi->max_frl_rate_per_lane);
We can just pass the connecter and drm_get_max_frl_rate can fill the respective fields.
> +}
> +
> static void drm_parse_ycbcr420_deep_color_info(struct drm_connector
> *connector,
> const u8 *db)
> {
> @@ -4902,6 +4948,11 @@ static void drm_parse_hdmi_forum_vsdb(struct
> drm_connector *connector,
> }
> }
>
> + if (hf_vsdb[7]) {
> + DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
> + drm_parse_hdmi_21_additional_fields(connector, hf_vsdb);
We can get rid of this extra wrapper.
> + }
> +
> drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); }
>
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
> 928136556174..f351bf10c076 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -207,6 +207,12 @@ struct drm_hdmi_info {
>
> /** @y420_dc_modes: bitmap of deep color support index */
> u8 y420_dc_modes;
> +
> + /** @max_frl_rate_per_lane: support fixed rate link */
> + u8 max_frl_rate_per_lane;
> +
> + /** @max_lanes: supported by sink */
> + u8 max_lanes;
> };
>
> /**
> --
> 2.17.1
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