Hi, Here are three improvements to the ingenic-drm driver. Patch 1 adds 30-bit RGB support for the SoCs that support it. Not much to see here. Patch 2 is here to allow the pixel clock to be re-set when the SoC's main PLL changes, which can happen at any time. We get a callback before and after the PLL clock rate is changed, which allows the ingenic-drm driver to synchronize the clock rate update with vblank. The synchronization mechanism is implemented with a mutex. I am not sure it is the best solution, there may be something better/simpler to do here, but in practice it works just fine. Patch 3 adds support for using a reserved memory area as storage space for GEM buffers. On memory-constrained devices, it is hard to find contiguous space even for a small 320x240 buffer, and sometimes dumb buffer allocation from userspace fails with -ENOMEM. Using a reserved memory area makes sure that there will always be space for our GEM buffers (provided they fit in the memory area). Cheers, -Paul Paul Cercueil (3): drm/ingenic: Add support for 30-bit modes drm/ingenic: Reset pixclock rate when parent clock rate changes drm/ingenic: Add support for reserved memory drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 109 +++++++++++++++++++--- drivers/gpu/drm/ingenic/ingenic-drm.h | 1 + 2 files changed, 99 insertions(+), 11 deletions(-) -- 2.28.0 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
