Hi Maxime, I love your patch! Yet something to improve: [auto build test ERROR on sunxi/sunxi/for-next] [also build test ERROR on soc/for-next xlnx/master linus/master v5.8-rc7 next-20200728] [cannot apply to mripard/sunxi/for-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Maxime-Ripard/drm-sun4i-backend-Support-alpha-property-on-lowest-plane/20200729-033432 base: https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git sunxi/for-next config: arm-defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> All errors (new ones prefixed by >>): drivers/gpu/drm/sun4i/sun4i_backend.c: In function 'sun4i_backend_atomic_check': >> drivers/gpu/drm/sun4i/sun4i_backend.c:592:57: error: expected statement before ')' token 592 | (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))) | ^ vim +592 drivers/gpu/drm/sun4i/sun4i_backend.c dd63250c55bf26 Maxime Ripard 2018-01-22 484 96180dde23b799 Maxime Ripard 2018-01-22 485 static int sun4i_backend_atomic_check(struct sunxi_engine *engine, 96180dde23b799 Maxime Ripard 2018-01-22 486 struct drm_crtc_state *crtc_state) 96180dde23b799 Maxime Ripard 2018-01-22 487 { 8f1f25534fff09 Maxime Ripard 2018-02-16 488 struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 }; dcf496a6a60873 Paul Kocialkowski 2018-07-19 489 struct sun4i_backend *backend = engine_to_sun4i_backend(engine); 96180dde23b799 Maxime Ripard 2018-01-22 490 struct drm_atomic_state *state = crtc_state->state; 96180dde23b799 Maxime Ripard 2018-01-22 491 struct drm_device *drm = state->dev; 96180dde23b799 Maxime Ripard 2018-01-22 492 struct drm_plane *plane; 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 493 unsigned int num_planes = 0; 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 494 unsigned int num_alpha_planes = 0; 96180dde23b799 Maxime Ripard 2018-01-22 495 unsigned int num_frontend_planes = 0; dcf496a6a60873 Paul Kocialkowski 2018-07-19 496 unsigned int num_alpha_planes_max = 1; 32463556a634f3 Maxime Ripard 2018-03-01 497 unsigned int num_yuv_planes = 0; 8f1f25534fff09 Maxime Ripard 2018-02-16 498 unsigned int current_pipe = 0; 8f1f25534fff09 Maxime Ripard 2018-02-16 499 unsigned int i; 96180dde23b799 Maxime Ripard 2018-01-22 500 96180dde23b799 Maxime Ripard 2018-01-22 501 DRM_DEBUG_DRIVER("Starting checking our planes\n"); 96180dde23b799 Maxime Ripard 2018-01-22 502 96180dde23b799 Maxime Ripard 2018-01-22 503 if (!crtc_state->planes_changed) 96180dde23b799 Maxime Ripard 2018-01-22 504 return 0; 96180dde23b799 Maxime Ripard 2018-01-22 505 96180dde23b799 Maxime Ripard 2018-01-22 506 drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) { 96180dde23b799 Maxime Ripard 2018-01-22 507 struct drm_plane_state *plane_state = 96180dde23b799 Maxime Ripard 2018-01-22 508 drm_atomic_get_plane_state(state, plane); 96180dde23b799 Maxime Ripard 2018-01-22 509 struct sun4i_layer_state *layer_state = 96180dde23b799 Maxime Ripard 2018-01-22 510 state_to_sun4i_layer_state(plane_state); 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 511 struct drm_framebuffer *fb = plane_state->fb; 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 512 struct drm_format_name_buf format_name; 96180dde23b799 Maxime Ripard 2018-01-22 513 ab6985108a53d5 Paul Kocialkowski 2018-11-23 514 if (!sun4i_backend_plane_is_supported(plane_state, ab6985108a53d5 Paul Kocialkowski 2018-11-23 515 &layer_state->uses_frontend)) ab6985108a53d5 Paul Kocialkowski 2018-11-23 516 return -EINVAL; ab6985108a53d5 Paul Kocialkowski 2018-11-23 517 ab6985108a53d5 Paul Kocialkowski 2018-11-23 518 if (layer_state->uses_frontend) { 96180dde23b799 Maxime Ripard 2018-01-22 519 DRM_DEBUG_DRIVER("Using the frontend for plane %d\n", 96180dde23b799 Maxime Ripard 2018-01-22 520 plane->index); 96180dde23b799 Maxime Ripard 2018-01-22 521 num_frontend_planes++; ae56bfbdad9b19 Paul Kocialkowski 2018-11-23 522 } else { ae56bfbdad9b19 Paul Kocialkowski 2018-11-23 523 if (fb->format->is_yuv) { ae56bfbdad9b19 Paul Kocialkowski 2018-11-23 524 DRM_DEBUG_DRIVER("Plane FB format is YUV\n"); ae56bfbdad9b19 Paul Kocialkowski 2018-11-23 525 num_yuv_planes++; ae56bfbdad9b19 Paul Kocialkowski 2018-11-23 526 } 96180dde23b799 Maxime Ripard 2018-01-22 527 } 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 528 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 529 DRM_DEBUG_DRIVER("Plane FB format is %s\n", 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 530 drm_get_format_name(fb->format->format, 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 531 &format_name)); d99008aab9f57d Maxime Ripard 2018-04-11 532 if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 533 num_alpha_planes++; 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 534 8f1f25534fff09 Maxime Ripard 2018-02-16 535 DRM_DEBUG_DRIVER("Plane zpos is %d\n", 8f1f25534fff09 Maxime Ripard 2018-02-16 536 plane_state->normalized_zpos); 8f1f25534fff09 Maxime Ripard 2018-02-16 537 8f1f25534fff09 Maxime Ripard 2018-02-16 538 /* Sort our planes by Zpos */ 8f1f25534fff09 Maxime Ripard 2018-02-16 539 plane_states[plane_state->normalized_zpos] = plane_state; 8f1f25534fff09 Maxime Ripard 2018-02-16 540 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 541 num_planes++; 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 542 } 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 543 8f1f25534fff09 Maxime Ripard 2018-02-16 544 /* All our planes were disabled, bail out */ 8f1f25534fff09 Maxime Ripard 2018-02-16 545 if (!num_planes) 8f1f25534fff09 Maxime Ripard 2018-02-16 546 return 0; 8f1f25534fff09 Maxime Ripard 2018-02-16 547 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 548 /* 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 549 * The hardware is a bit unusual here. 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 550 * 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 551 * Even though it supports 4 layers, it does the composition 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 552 * in two separate steps. 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 553 * 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 554 * The first one is assigning a layer to one of its two 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 555 * pipes. If more that 1 layer is assigned to the same pipe, 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 556 * and if pixels overlaps, the pipe will take the pixel from 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 557 * the layer with the highest priority. 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 558 * 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 559 * The second step is the actual alpha blending, that takes dcf496a6a60873 Paul Kocialkowski 2018-07-19 560 * the two pipes as input, and uses the potential alpha 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 561 * component to do the transparency between the two. 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 562 * dcf496a6a60873 Paul Kocialkowski 2018-07-19 563 * This two-step scenario makes us unable to guarantee a 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 564 * robust alpha blending between the 4 layers in all 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 565 * situations, since this means that we need to have one layer 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 566 * with alpha at the lowest position of our two pipes. 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 567 * dcf496a6a60873 Paul Kocialkowski 2018-07-19 568 * However, we cannot even do that on every platform, since dcf496a6a60873 Paul Kocialkowski 2018-07-19 569 * the hardware has a bug where the lowest plane of the lowest dcf496a6a60873 Paul Kocialkowski 2018-07-19 570 * pipe (pipe 0, priority 0), if it has any alpha, will dcf496a6a60873 Paul Kocialkowski 2018-07-19 571 * discard the pixel data entirely and just display the pixels dcf496a6a60873 Paul Kocialkowski 2018-07-19 572 * in the background color (black by default). 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 573 * dcf496a6a60873 Paul Kocialkowski 2018-07-19 574 * This means that on the affected platforms, we effectively dcf496a6a60873 Paul Kocialkowski 2018-07-19 575 * have only three valid configurations with alpha, all of dcf496a6a60873 Paul Kocialkowski 2018-07-19 576 * them with the alpha being on pipe1 with the lowest dcf496a6a60873 Paul Kocialkowski 2018-07-19 577 * position, which can be 1, 2 or 3 depending on the number of dcf496a6a60873 Paul Kocialkowski 2018-07-19 578 * planes and their zpos. 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 579 */ dcf496a6a60873 Paul Kocialkowski 2018-07-19 580 dcf496a6a60873 Paul Kocialkowski 2018-07-19 581 /* For platforms that are not affected by the issue described above. */ dcf496a6a60873 Paul Kocialkowski 2018-07-19 582 if (backend->quirks->supports_lowest_plane_alpha) dcf496a6a60873 Paul Kocialkowski 2018-07-19 583 num_alpha_planes_max++; dcf496a6a60873 Paul Kocialkowski 2018-07-19 584 dcf496a6a60873 Paul Kocialkowski 2018-07-19 585 if (num_alpha_planes > num_alpha_planes_max) { 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 586 DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n"); 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 587 return -EINVAL; 96180dde23b799 Maxime Ripard 2018-01-22 588 } 96180dde23b799 Maxime Ripard 2018-01-22 589 8f1f25534fff09 Maxime Ripard 2018-02-16 590 /* We can't have an alpha plane at the lowest position */ dcf496a6a60873 Paul Kocialkowski 2018-07-19 591 if (!backend->quirks->supports_lowest_plane_alpha && dcf496a6a60873 Paul Kocialkowski 2018-07-19 @592 (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))) 8f1f25534fff09 Maxime Ripard 2018-02-16 593 return -EINVAL; 8f1f25534fff09 Maxime Ripard 2018-02-16 594 8f1f25534fff09 Maxime Ripard 2018-02-16 595 for (i = 1; i < num_planes; i++) { 8f1f25534fff09 Maxime Ripard 2018-02-16 596 struct drm_plane_state *p_state = plane_states[i]; 8f1f25534fff09 Maxime Ripard 2018-02-16 597 struct drm_framebuffer *fb = p_state->fb; 8f1f25534fff09 Maxime Ripard 2018-02-16 598 struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state); 8f1f25534fff09 Maxime Ripard 2018-02-16 599 8f1f25534fff09 Maxime Ripard 2018-02-16 600 /* 8f1f25534fff09 Maxime Ripard 2018-02-16 601 * The only alpha position is the lowest plane of the 8f1f25534fff09 Maxime Ripard 2018-02-16 602 * second pipe. 8f1f25534fff09 Maxime Ripard 2018-02-16 603 */ d99008aab9f57d Maxime Ripard 2018-04-11 604 if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) 8f1f25534fff09 Maxime Ripard 2018-02-16 605 current_pipe++; 8f1f25534fff09 Maxime Ripard 2018-02-16 606 8f1f25534fff09 Maxime Ripard 2018-02-16 607 s_state->pipe = current_pipe; 8f1f25534fff09 Maxime Ripard 2018-02-16 608 } 8f1f25534fff09 Maxime Ripard 2018-02-16 609 32463556a634f3 Maxime Ripard 2018-03-01 610 /* We can only have a single YUV plane at a time */ 32463556a634f3 Maxime Ripard 2018-03-01 611 if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) { 32463556a634f3 Maxime Ripard 2018-03-01 612 DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n"); 32463556a634f3 Maxime Ripard 2018-03-01 613 return -EINVAL; 32463556a634f3 Maxime Ripard 2018-03-01 614 } 32463556a634f3 Maxime Ripard 2018-03-01 615 96180dde23b799 Maxime Ripard 2018-01-22 616 if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) { 96180dde23b799 Maxime Ripard 2018-01-22 617 DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n"); 96180dde23b799 Maxime Ripard 2018-01-22 618 return -EINVAL; 96180dde23b799 Maxime Ripard 2018-01-22 619 } 96180dde23b799 Maxime Ripard 2018-01-22 620 32463556a634f3 Maxime Ripard 2018-03-01 621 DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n", 32463556a634f3 Maxime Ripard 2018-03-01 622 num_planes, num_alpha_planes, num_frontend_planes, 32463556a634f3 Maxime Ripard 2018-03-01 623 num_yuv_planes); 65f7fa3a3fcbdb Maxime Ripard 2017-06-26 624 96180dde23b799 Maxime Ripard 2018-01-22 625 return 0; 96180dde23b799 Maxime Ripard 2018-01-22 626 } 96180dde23b799 Maxime Ripard 2018-01-22 627 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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