Re: [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI

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On 31.07.2012 16:02, Alex Deucher wrote:
On Tue, Jul 31, 2012 at 7:48 AM, Christian König
<deathsimple@xxxxxxxxxxx> wrote:
The sixteen bank case wasn't handled here, leading to GPU
crashes because of userspace miscalculation.
You mean a GPU hang or a segfault in userspace?  IIRC, from the hw
perspective numbers of banks over 8 are considered 8 for tiling.
Well it was a GPU segfault :) The GPU was accessing memory regions that weren't VM mapped.

As far as i could figure it out it wasn't happy with the alignment of the color buffer. The number of banks we used for that calculation seemed to be different from what the kernel programmed into the tiling config registers. So I tried changing it from 8 to 16 and hurray it started working (ok, more or less currently digging into the next problem).

It is possible that this is just masquerading another bug, but as far as I can see it is the most logical explanation.

Why are 16 banks equal to 8 banks on the hw side?

Christian.


Alex

Signed-off-by: Christian König <deathsimple@xxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
---
  drivers/gpu/drm/radeon/si.c |   16 ++++++++++++----
  1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 0b02792..0182fc8 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device *rdev)
                 /* XXX what about 12? */
                 rdev->config.si.tile_config |= (3 << 0);
                 break;
-       }
-       if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
-               rdev->config.si.tile_config |= 1 << 4;
-       else
+       }
+       switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
+       case 0: /* four banks */
                 rdev->config.si.tile_config |= 0 << 4;
+               break;
+       case 1: /* eight banks */
+               rdev->config.si.tile_config |= 1 << 4;
+               break;
+       case 2: /* sixteen banks */
+       default:
+               rdev->config.si.tile_config |= 2 << 4;
+               break;
+       }
         rdev->config.si.tile_config |=
                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
         rdev->config.si.tile_config |=
--
1.7.9.5

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