On Thu, May 24, 2012 at 09:08:59PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > MI display flips can't handle some changes in the framebuffer > format or layout. Return an error in such cases. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Queued for -next, thanks for the patch. I've punted on the others, hoping for a few i-g-t tests (and maybe someone else that could review them). Safe for the uninitialized stack var patch and this one, because we need this check to fix up gen4+ tileoffset limitations. Yours, Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++ > 1 files changed, 13 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index f4338cb..72ac2f9 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6217,6 +6217,19 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > unsigned long flags; > int ret; > > + /* Can't change pixel format via MI display flips. */ > + if (fb->pixel_format != crtc->fb->pixel_format) > + return -EINVAL; > + > + /* > + * TILEOFF/LINOFF registers can't be changed via MI display flips. > + * Note that pitch changes could also affect these register. > + */ > + if (INTEL_INFO(dev)->gen > 3 && > + (fb->offsets[0] != crtc->fb->offsets[0] || > + fb->pitches[0] != crtc->fb->pitches[0])) > + return -EINVAL; > + > work = kzalloc(sizeof *work, GFP_KERNEL); > if (work == NULL) > return -ENOMEM; > -- > 1.7.3.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@xxxxxxxx Mobile: +41 (0)79 365 57 48 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
