On Thu, Jun 14, 2012 at 7:14 PM, Wouter M. Koolen <W.M.Koolen-Wijkstra@xxxxxx> wrote: > On 06/14/2012 03:48 PM, Wouter M. Koolen wrote: >> >> In the mean while I will redo the bisect. > > Hi guys, > > I did a bisect on the actual problem (and not on the maybe-related second > error message). It results in 092945e11c5b84f66dd08f0b87fb729715d377bc: > > Author: Adam Jackson <ajax@xxxxxxxxxx> 2011-07-26 20:39:45 > Committer: Daniel Vetter <daniel.vetter@xxxxxxxx> 2012-01-17 15:46:56 > Parent: 6919132e7a307b1f181d7655b3ef64cc7581a5ef (drm/i915/dp: Tweak auxch > clock divider for PCH) > Branches: linux-3.4.y, remotes/origin/linux-3.4.y, remotes/origin/master > Follows: v3.2-rc6 > Precedes: v3.4-rc1 > > drm/i915/dp: Use auxch precharge value of 5 everywhere > > The default in the Sandybridge docs is 5, as on Ironlake, and I have no > reason to believe 3 would work any better. > > Signed-off-by: Adam Jackson <ajax@xxxxxxxxxx> > Acked-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> > > I guess there is your reason for 3 :) > > Any advice on how to proceed would be very helpful. Well, can you revert this patch (or just replace the 5 with 3 in the code) on top of latest 3.4.x and test whether this is indeed the cause of your regression? Just to make sure that we have the right culprit. Thanks, Daniel -- Daniel Vetter daniel.vetter@xxxxxxxx - +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
