On 08. 11. 19 18:59, Laurent Pinchart wrote:
> Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
> the DisplayPort connector.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> ---
> .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> index 93ce7eb81498..4656f25b6b04 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> @@ -13,6 +13,7 @@
> #include "zynqmp-clk.dtsi"
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy.h>
>
> / {
> model = "ZynqMP ZCU106 RevA";
> @@ -69,6 +70,17 @@
> status = "okay";
> };
>
> +&dpdma {
> + status = "okay";
> +};
> +
> +&dpsub {
> + status = "okay";
> + phy-names = "dp-phy0", "dp-phy1";
> + phys = <&lane1 PHY_TYPE_DP 0 3 27000000>,
> + <&lane0 PHY_TYPE_DP 1 3 27000000>;
It is aligned with stuff in Xilinx tree.
I think that putting any clock value here is wrong.
It should really be pointing to &clk whatever it is.
Then you can support more cases where clock doesn't need to be fixed and
it is also aligned with clock binding.
> +};
> +
> /* fpd_dma clk 667MHz, lpd_dma 500MHz */
> &fpd_dma_chan1 {
> status = "okay";
> @@ -503,6 +515,10 @@
> no-1-8-v;
> };
>
> +&serdes {
> + status = "okay";
> +};
> +
> &uart0 {
> status = "okay";
> };
>
M
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