On 30/09/2019 09:45, Tomi Valkeinen wrote:
Hi,
On 27/09/2019 18:47, Tomi Valkeinen wrote:
On 27/09/2019 18:37, Tero Kristo wrote:
If you can provide details about what clock framework / driver does
wrong (sample clk_set_xyz call sequence, expected results via
clk_get_xyz, and what fails), I can take a look at it. Just reporting
arbitrary display driver issues I won't be able to debug at all (I
don't have access to any of the displays, nor do I want to waste time
debugging them without absolutely no knowledge whatsoever.)
I used your hack patches to allow changing rates via debugfs. And set
dss1_alwon_fck_3430es2 to 27000000 or 27870967. The end result was
that DSS gets some very high clock from dss1_alwon_fck_3430es2, as the
frame rate jumps to many hundreds fps.
So, these numbers are not real, but to give the idea what I saw.
Running first with 50 MHz, I can see, say, 40 fps. Then I set the
clock to 30 MHz, and fps dropped to, say, 30fps, as expected with
lower clock. Then I set the clock to 27MHz (or the other one),
expecting a bit lower fps, but instead I saw hundreds of fps.
I don't know if there's any other way to observe the wrong clock rate
but have the dss enabled and running kmstest or similar. I can help
you set that up next week, should be trivial. You don't need a display
for that.
Here's how to reproduce. I have the attached patches. Three of them are
the clk-debug ones, and one of mine to make it easy to test without a
display, and without underflow flood halting the device. There are on
top of v5.3. Kernel config also attached.
kmstest is from kms++ project (https://github.com/tomba/kmsxx). It
should be straightforward to compile, but kmstest binary is also
included in TI's rootfs.
Ok, I ignored all your test code and just fiddled with my trusty clk
debugfs patches. I don't like debugging with test code I have no
experience with. :)
Anyways, it seems the dpll4_m4_ck max divider value is wrong, it only
accepts values upto 16 at least on my board. The setting for this in DT
is 32, and it is most likely SoC specific what happens if you write an
invalid value to the divider.
The best action here is probably to drop the max-div value for this
clock to 16. Can someone check this with their display setup and see
what happens? Attached patch should do the trick.
-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>From 28bfaaa3747e9033b6d4cd7bb06eb72dc04580a5 Mon Sep 17 00:00:00 2001
From: Tero Kristo <t-kristo@xxxxxx>
Date: Mon, 30 Sep 2019 11:49:39 +0300
Subject: [PATCH 1/1] ARM: dts: omap3: fix DPLL4 M4 divider max value
The maximum divider value for DPLL4 M4 divider appears wrong. For most
OMAP3 family SoCs this is 16, but it is defined as 32, which is maybe
only valid for omap36xx. To avoid any overflows in trying to write this
register, set the max to 16 for all omap3 family.
Signed-off-by: Tero Kristo <t-kristo@xxxxxx>
---
arch/arm/boot/dts/omap3xxx-clocks.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 685c82a9d03e..0656c32439d2 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -416,7 +416,7 @@
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll4_ck>;
- ti,max-div = <32>;
+ ti,max-div = <16>;
reg = <0x0e40>;
ti,index-starts-at-one;
};
--
2.17.1
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