The bus behind the board's PCIe core has DMA addressing limitations. Add an empty 'dma-ranges' property on all PCIe bus descriptions to inform the OF core that a translation is due further down the line. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@xxxxxxx> --- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index fd6036b7865c..2c41cfc66bb9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -640,6 +640,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + dma-ranges; num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; @@ -661,6 +662,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + dma-ranges; num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; @@ -682,6 +684,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + dma-ranges; num-viewport = <256>; bus-range = <0x0 0xff>; msi-parent = <&its>; @@ -703,6 +706,7 @@ #size-cells = <2>; device_type = "pci"; dma-coherent; + dma-ranges; num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; -- 2.23.0 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
