Hi, Jitao: On Thu, 2019-06-27 at 10:58 +0800, Jitao Shi wrote: > Update device tree binding documentation for the dsi for > Mediatek MT8183 SoCs. > > Signed-off-by: Jitao Shi <jitao.shi@xxxxxxxxxxxx> > Acked-by: Rob Herring <robh@xxxxxxxxxx> This version is different than previous version, so I think you should remove the Acked-by tag. Or Rob could give a tag again on this patch. Regards, CK > --- > .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > index fadf327c7cdf..a19a6cc375ed 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > @@ -7,7 +7,7 @@ channel output. > > Required properties: > - compatible: "mediatek,<chip>-dsi" > - the supported chips are mt2701 and mt8173. > + the supported chips are mt2701, mt8173 and mt8183. > - reg: Physical base address and length of the controller's registers > - interrupts: The interrupt signal from the function block. > - clocks: device clocks > @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. > > Required properties: > - compatible: "mediatek,<chip>-mipi-tx" > - the supported chips are mt2701 and mt8173. > + the supported chips are mt2701, mt8173 and mt8183. > - reg: Physical base address and length of the controller's registers > - clocks: PLL reference clock > - clock-output-names: name of the output clock line to the DSI encoder _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
