https://bugs.freedesktop.org/show_bug.cgi?id=48880 --- Comment #24 from Alex Deucher <agd5f@xxxxxxxxx> 2012-04-19 08:20:03 PDT --- (In reply to comment #23) > > The trick is testing a given version of the chip to the death and finding the > frequency limits of the inner loop of the pll. I have always managed to fully > clamp down pll ranges with a halfway decent CRT. It does take time and a > structured approach though. Even then you still hit problematic monitors. CRTs are usually pretty forgiving; it's usually digital monitors that have problems. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
