On Fri, Jun 14, 2019 at 10:29 AM Robert Chiras <robert.chiras@xxxxxxx> wrote: > The GPIO is active high, and the above sequence was received from the > panel vendor in the following form: > SET_RESET_PIN(1); > MDELAY(10); > SET_RESET_PIN(0); > MDELAY(5); > SET_RESET_PIN(1); > MDELAY(20); > I got rid of the first transition to high since seemed redundant. > Also, according to the manual reference, the RSTB pin needs to be > active high while operating the display. That's exactly my point :-) In normal operation the GPIO reset needs to be high. During reset the GPIO reset needs to be low., which means that the GPIO reset is "active low". So you should invert both the dts and the driver to behave correctly. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
