On Wed, May 29, 2019 at 7:02 AM Ville Syrjala
<ville.syrjala@xxxxxxxxxxxxxxx> wrote:
>
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> From VESA EDID implementation guide v1.0:
> "For EDID version 1 revision 2 or earlier data structures when offset 14h
> bit 7 is set to one, the value of bits 6-0 are undefined, and therefore
> cannot be interpreted to mean anything."
>
> And since EDID 1.4 redefines that bit let's consult it only for
> EDID 1.3.
>
> Cc: Mario Kleiner <mario.kleiner.de@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/drm_edid.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index dd601ed6a30e..c3296a72fff9 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4569,8 +4569,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
> * tells us to assume 8 bpc color depth if the EDID doesn't have
> * extensions which tell otherwise.
> */
> - if ((info->bpc == 0) && (edid->revision < 4) &&
> - (edid->input & DRM_EDID_DIGITAL_DFP_1_X)) {
> + if (info->bpc == 0 && edid->revision == 3 &&
> + edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
> info->bpc = 8;
> DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
> connector->name, info->bpc);
> --
> 2.21.0
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/dri-devel
