On Thu, May 16, 2019 at 07:40:13PM +0530, Uma Shankar wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> This patch enables infoframes on GLK+ to be
> used to send HDR metadata to HDMI sink.
>
> v2: Addressed Shashank's review comment.
>
> v3: Addressed Shashank's review comment.
>
> v4: Added Shashank's RB.
>
> v5: Dropped hdr_metadata_change check while modeset, as per
> Ville's suggestion.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> Reviewed-by: Shashank Sharma <shashank.sharma@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_hdmi.c | 19 +++++++++++++++----
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e97c47f..d3f5510 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4694,6 +4694,7 @@ enum {
> #define VIDEO_DIP_FREQ_MASK (3 << 16)
> /* HSW and later: */
> #define DRM_DIP_ENABLE (1 << 28)
Just noticed this duplicate bit definition. The new name looks to
be more in line with the names of the other bits, so I would just
kill this old bogus defintion while at it.
> +#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
> #define PSR_VSC_BIT_7_SET (1 << 27)
> #define VSC_SELECT_MASK (0x3 << 25)
> #define VSC_SELECT_SHIFT 25
> @@ -8146,6 +8147,7 @@ enum {
> #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
> #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
> #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
> +#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
> #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
> #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
> #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
> @@ -8159,6 +8161,7 @@ enum {
> #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
> #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
> #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
> +#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
> #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
> #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
> #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
> @@ -8184,6 +8187,7 @@ enum {
> #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
> #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
> #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
> +#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
> #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
> #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index d3b8e09..8bd7c07 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -152,6 +152,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
> return VIDEO_DIP_ENABLE_SPD_HSW;
> case HDMI_INFOFRAME_TYPE_VENDOR:
> return VIDEO_DIP_ENABLE_VS_HSW;
> + case HDMI_INFOFRAME_TYPE_DRM:
> + return VIDEO_DIP_ENABLE_DRM_GLK;
> default:
> MISSING_CASE(type);
> return 0;
> @@ -177,6 +179,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
> return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
> case HDMI_INFOFRAME_TYPE_VENDOR:
> return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
> + case HDMI_INFOFRAME_TYPE_DRM:
> + return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
> default:
> MISSING_CASE(type);
> return INVALID_MMIO_REG;
> @@ -560,10 +564,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
> + u32 mask;
>
> - return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
> - VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> - VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
> + mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
> + VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> + VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
> +
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + mask |= VIDEO_DIP_ENABLE_DRM_GLK;
> +
> + return val & mask;
> }
>
> static const u8 infoframe_type_to_idx[] = {
> @@ -1193,7 +1203,8 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
>
> val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> - VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
> + VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
> + VIDEO_DIP_ENABLE_DRM_GLK);
>
> if (!enable) {
> I915_WRITE(reg, val);
> --
> 1.9.1
--
Ville Syrjälä
Intel
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