Hi, We've had for quite some time to hack around in our drivers to take into account the fact that our DMA accesses are not done through the parent node, but through another bus with a different mapping than the CPU for the RAM (0 instead of 0x40000000 for most SoCs). After some discussion after the submission of a camera device suffering of the same hacks, I've decided to put together a serie that introduce a special interconnect name called "dma" that that allows to express the DMA relationship between a master and its bus, even if they are not direct parents in the DT. Let me know what you think, Maxime Changes from v1: - Change to use the now merged interconnect bindings - Move the DMA parent retrieval logic to its own function - Rebase on top of 5.0 Maxime Ripard (7): dt-bindings: interconnect: Add a dma interconnect name dt-bindings: bus: Add binding for the Allwinner MBUS controller of: address: Add parent pointer to the __of_translate_address args of: address: Add support for the dma-parent property drm/sun4i: Rely on dma-parent for our RAM offset clk: sunxi-ng: sun5i: Export the MBUS clock ARM: dts: sun5i: Add the MBUS controller Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt | 36 +++++- Documentation/devicetree/bindings/interconnect/interconnect.txt | 3 +- arch/arm/boot/dts/sun5i.dtsi | 13 ++- drivers/clk/sunxi-ng/ccu-sun5i.h | 4 +- drivers/gpu/drm/sun4i/sun4i_backend.c | 28 +++- drivers/of/address.c | 49 +++++-- include/dt-bindings/clock/sun5i-ccu.h | 2 +- 7 files changed, 114 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt base-commit: 87e87c7b0eeb3c9e08cdfe28fd540247bdf31ef5 -- git-series 0.9.1 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
