On Thu, Mar 29, 2012 at 04:46:39PM +0800, Daniel Kurtz wrote: > On Thu, Mar 29, 2012 at 2:41 AM, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > > On Thu, 29 Mar 2012 02:26:34 +0800, Daniel Kurtz <djkurtz@xxxxxxxxxxxx> wrote: > >> The GMBUS controller GMBUS3 register is double-buffered. Take advantage > >> of this by writing two 4-byte words before the first wait for HW_RDY. > >> This helps keep the GMBUS controller from becoming idle during long writes. > >> > >> Signed-off-by: Daniel Kurtz <djkurtz@xxxxxxxxxxxx> > > > > "For byte counts that are greater than four bytes, this register will be > > written with subsequent data only after the HW_RDY status bit is set" > > > > Hmm, I had interpretted that as should only be. But if you take into > > account that the register is indeed double-buffered, it does make sense > > that the hardware itself is only updated after the HW_RDY signal. > > Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > In fact, during my experiments using the GMBUS interrupts, the HW_RDY > interrupt would only trigger for transactions > 4 bytes after 2 writes > to GMBUS3. I think that's rather important information. Can you add this to your commit message? -Daniel -- Daniel Vetter Mail: daniel@xxxxxxxx Mobile: +41 (0)79 365 57 48 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
